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this is information on a product in full production. september 2013 doc id 14642 rev 11 1/142 1 spc563m64l5, spc563m64l7 spc563m60l5p, spc563m60l7p 32-bit power architecture ? based mcu for automotive powertrain applications datasheet ? production data features single issue, 32-bit power architecture ? book e compliant e200z335 cpu core complex ? includes variable length encoding (vle) enhancements for code size reduction 32-channel direct memory access controller (dma) interrupt controller (intc) capable of handling 364 selectable-priority interrupt sources: 191 peripheral interrupt sources, 8 software interrupts and 165 reserved interrupts. frequency-modulated phase-locked loop (fmpll) calibration external bus interface (ebi) (a) system integration unit (siu) up to 1.5 mbyte on-chip flash with flash controller ? fetch accelerator for single cycle flash access @80 mhz up to 94 kbyte on-chip static ram (including up to 32 kbyte standby ram) boot assist module (bam) 32-channel second-generation enhanced time processor unit (etpu) ? 32 standard etpu channels ? architectural enhancements to improve code efficiency and added flexibility 16-channels enhanced modular input-output system (emios) enhanced queued analog-to-digital converter (eqadc) decimation filter (part of eqadc) silicon die temperature sensor 2 deserial serial peripheral interface (dspi) modules (compatible with microsecond bus) 2 enhanced serial communication interface (esci) modules co mpatible with lin 2 controller area network (flexcan) modules that support can 2.0b nexus port controller (npc) per ieee-isto 5001-2003 standard ieee 1149.1 (jtag) support nexus interface on-chip voltage regulator controller that provides 1.2 v and 3.3 v internal supplies from a 5 v external source. designed for lqfp100, lqfp144, lqfp176 and lbga208. a. the external bus interface is only accessible when using the calibration tool . it is not available on production packages. lfbga208 17 mm x 17 mm x1.5mm 144 lqfp 20 mm x 20 mm 100 lqfp 14 mm x 14 mm 176 lqfp 24 mm x 24 m m table 1. device summary memory flash size part number package: lqfp100 package: lqfp144 package: lqfp176 package: lbga208 1536 kbyte ? spc563m64l5 spc563m64l7 ? 1024 kbyte ? spc563m60l5p spc563m60l7p ? www.st.com
contents spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 2/142 doc id 14642 rev 11 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 spc563mxx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 spc563mxx feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.1 e200z335 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.2 crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.3 edma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.4 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.5 fmpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.6 calibration ebi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.7 siu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.8 ecsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.9 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.10 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.11 bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.12 emios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.13 etpu2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.14 eqadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.15 dspi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.16 esci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.17 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.18 system timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.19 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.3.20 debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 spc563mxx series architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.2 block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p contents doc id 14642 rev 11 3/142 3.2 lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 lqfp176 pinout (spc563m64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 lqfp176 pinout (spc563m60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5 lbga208 ballmap (spc563m64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6 signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7 signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.1 general notes for specifications at maximum junction temperature . . . 76 4.4 electromagnetic interference (emi) characte ristics . . . . . . . . . . . . . . . . . 79 4.5 electromagnetic static discharge (esd) characteristics . . . . . . . . . . . . . . 79 4.6 power management control (pmc) and power on reset (por) electrical specifications 80 4.6.1 regulator example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.6.2 recommended power transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.7 power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.8 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.9 i/o pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.9.1 i/o pad vrc33 current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.9.2 lvds pad specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.10 oscillator and pllmrfm electrical characteristics . . . . . . . . . . . . . . . . . 97 4.11 temperature sensor electrical characteristic s . . . . . . . . . . . . . . . . . . . . . 99 4.12 eqadc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.13 platform flash controller electrical charac teristics . . . . . . . . . . . . . . . . . 102 4.14 flash memory electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.15 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.15.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.16 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.16.1 ieee 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.16.2 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.16.3 calibration bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.16.4 emios timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
contents spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 4/142 doc id 14642 rev 11 4.16.5 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.16.6 eqadc ssi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.2.1 lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.2.2 lqfp144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.2.3 lqfp176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.2.4 lbga208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p list of tables doc id 14642 rev 11 5/142 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc563mxx family device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. spc563mxx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 4. spc563mx signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5. pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 6. signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 7. spc563mx power/ground segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 10. thermal characteristics for 100-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 11. thermal characteristics for 144-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 12. thermal characteristics for 176-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 13. thermal characteristics for 208-pin lbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 14. emi testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 15. esd ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 16. pmc operating conditions an d external regulators supply voltage . . . . . . . . . . . . . . . . . . 80 table 17. pmc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 18. required external pmc component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 19. network 1 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 20. network 2 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 21. network 3 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 22. recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 23. power sequence pin states for fast pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 24. power sequence pin states for medium, slow and multi-voltage pads . . . . . . . . . . . . . . . . 87 table 25. dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 26. i/o pad average i dde specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 27. i/o pad v rc33 average i dde specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 28. v rc33 pad average dc current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 29. dspi lvds pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 30. pllmrfm electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 31. temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 32. eqadc conversion specifications (operating) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 33. apc, rwsc, wwsc settings vs. frequency of operation . . . . . . . . . . . . . . . . . . . . . . . . 102 table 34. program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 table 35. flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 36. pad ac specifications (5.0 v) , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 37. pad ac specifications (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 38. pad ac specifications (1.8 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 39. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 08 table 40. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 41. calibration bus operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 42. emios timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 43. dspi timing , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 44. eqadc ssi timing characteristics (pads at 3.3 v or at 5.0 v) . . . . . . . . . . . . . . . . . . . . . 123 table 45. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 46. lqfp176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 47. lbga208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 48. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
list of figures spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 6/142 doc id 14642 rev 11 list of figures figure 1. spc563mxx series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 figure 2. 100-pin lqfp pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 3. 144-pin lqfp pinout (top view; all 144-pin devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 4. 176-pin lqfp pinout (spc563m64; top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 5. 176-pin lqfp pinout (spc563m60; top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6. 208-pin lbga ballmap (spc563m64; top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 7. core voltage regulator controller external components preferred configuration . . . . . . . . . 84 figure 8. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 9. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 10. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 11. jtag jcomp timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 12. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 13. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 14. nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 15. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 16. clkout timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 17. synchronous output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 18. synchronous input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 19. ale signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 20. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 21. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 22. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 23. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 24. dspi modified transfer format timing ? master, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . 121 figure 25. dspi modified transfer format timing ? master, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . 121 figure 26. dspi modified transfer format timing ? slave, cpha =0 . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 27. dspi modified transfer format timing ? slave, cpha =1 . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 28. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23 figure 29. eqadc ssi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 30. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 31. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 32. lqfp176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 33. lbga208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 34. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 34
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p introduction doc id 14642 rev 11 7/142 1 introduction 1.1 document overview this document provides an overview and describes the features of the spc563mxx series of microcontroller units (mcus). for functional c haracteristics, refer to the device reference manual. electrical specifications and package mechanical drawings are included in this device data sheet. pin assignments can be found in both the reference manual and data sheet. 1.2 description these 32-bit automotive microcontrollers are a family of system-on-ch ip (soc) devices that contain many new features coupled with high performance 90 nm cmos technology to provide substantial reduction of cost per feature and significant performance improvement. the advanced and cost-efficient host processor core of this automotive controller family is built on power architecture ? technology. this family contains enhancements that improve the architecture?s fit in embedded applications, includes additional instruction support for digital signal processing (dsp), integrates technologies?such as an enhanced time processor unit, enhanced queued analog-to-digital converter, controller area network, and an enhanced modular input-output system?that are important for today?s lower-end powertrain applications. the device has a single level of memory hierarchy consisting of up to 94 kb on-chip sram and up to 1.5 mb of internal flash memory. the device also has an external bus interface (ebi) for ?calibration?.
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 8/142 doc id 14642 rev 11 2 overview this document provides electrical specific ations, pin assignments, and package diagrams for the spc563mxx series of microcontroller un its (mcus). for functional characteristics, refer to the spc563mxx microcontroller reference manual. the spc563mxx series microcontrollers are system-on-chip devices that are built on power architecture ? technology and: are 100% user-mode compatible with the power architecture instruction set contain enhancements that improve the architecture?s fit in embedded applications include additional instruction support for digital signal processing (dsp) integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, controller area network, and an enhanced modular input- output system operating parameters ? fully static operation, 0 mhz ? 80 mhz (plus 2% frequency modulation - 82 mhz) ? ?40 ? c ? 150 ? c junction temperature operating range ? low power design less than 400 mw power dissipation (nominal) designed for dynamic power management of core and peripherals software controlled clock gating of peripherals low power stop mode, with all clocks stopped ? fabricated in 90 nm process ? 1.2 v internal logic high performance e200z335 core processor advanced microcontroller bus architecture (amba) crossbar switch (xbar) enhanced direct memory access (edma) controller interrupt controller (intc) ? 191 peripheral interrupt request sources, plus 165 reserved positions ? low latency?three clocks from receipt of interrupt request from peripheral to interrupt request to processor frequency modulating phase-locked loop (fmpll) calibration bus interface (ebi) (availa ble only in the calibration package) system integration unit (siu) centralizes control of pads, gpio pins and external interrupts. error correction status module (ecsm) provides configurable error-correcting codes (ecc) reporting up to 1.5 mb on-chip flash memory up to 94 kb on-chip static ram boot assist module (bam) enables and manages the transition of mcu from reset to user code execution from internal flash memory, external memory on the calibration bus or download and execution of code via flexcan or esci.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 9/142 periodic interrupt timer (pit) ? 32-bit wide down counter with automatic reload ? 4 channels clocked by system clock ? 1 channel clocked by crystal clock system timer module (stm) ? 32-bit up counter with 8-bit prescaler ? clocked from system clock ? 4 channel timer compare hardware software watchdog timer (swt) 32-bit timer enhanced modular i/o system (emios) ? 16 standard timer channels (up to 14 channels connected to pins in lqfp144) ? 24-bit timer resolution second-generation enhanced time processor unit (etpu2) ? high level assembler/compiler ? enhancements to make ?c ? compiler more efficient ? new ?engine relative? addressing mode enhanced queued a/d converter (eqadc) ? 2 independent on-chip rsd cyclic adcs ? up to 34 input channels available to the two on-chip adcs ? 4 pairs of differential analog input channels 2 deserial serial peripheral interface modules (dspi) ? spi provides full duplex communication ports with interrupt and dma request support ? deserial serial interface (dsi) achieves pin reduction by hardware serialization and deserialization of etpu, emios channels and gpio 2 enhanced serial communication interface (esci) modules 2 flexcan modules nexus port controller (npc) pe r ieee-isto 5001-2003 standard ieee 1149.1 jtag controller (jtagc)
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 10/142 doc id 14642 rev 11 2.1 device comparison table 2. spc563mxx family device summary feature spc563m64 spc563m60p spc563m54p flash memory size (kb) 1536 1024 768 total sram size (kb) 94 64 48 standby sram size (kb) 32 32 24 processor core 32-bit e200z335 with spe and fpu support 32-bit e200z335 with spe and fpu support 32-bit e200z335 with spe and fpu support core frequency (mhz) 64/80 40/64/80 40/64 calibration bus width (1) 16 bits 16 bits ? dma (direct memory access) channels 32 32 32 emios (enhanced modular input-output system) channels 16 16 16 eqadc (enhanced queued analog-to-digital converter) channels (on-chip) up to 34 (2) up to 34 (2) up to 32 (2) esci (serial communication interface) 2 2 2 dspi (deserial serial peripheral interface) 2 2 2 microsecond channel compatible interface 2 2 2 etpu (enhanced time processor unit) yes yes yes channels 32 32 32 code memory (kb) 14 14 14 parameter ram (kb) 3 3 3 flexcan (controller area network) (3) 222 fmpll (frequency-modulated phase-locked loop) yes yes yes intc (interrupt controller) channels 364 (4) 364 (4) 364 (4) jtag controller yes yes yes ndi (nexus development interface) level class 2+ class 2+ class 2+ non-maskable interrupt and critical interrupt yes yes yes pit (periodic interrupt timers) 5 5 5 task monitor timer 4 channels 4 channels 4 channels temperature sensor yes yes yes windowing software watchdog yes yes yes packages lqfp144 lqfp176 lqfp100 lqfp144 lqfp176 lqfp100 lqfp144 1. calibration package only. 2. the 176-pin and 208-pin packages have 34 input c hannels; 144-pin package has 32; 100-pin package has 23. 3. one flexcan module has 64 message buffe rs; the other has 32 message buffers.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 11/142 4. 165 interrupt channels are reserved for compatibility with fu ture devices. this device has 191 peripheral interrupt sources plus 8 software interrupts available to the user.
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 12/142 doc id 14642 rev 11 2.2 spc563mxx features operating parameters ? fully static operation, 0 mhz ? 80 mhz (plus 2% frequency modulation - 82 mhz) ? ?40 ? c to 150 ? c junction temperature operating range ? low power design less than 400 mw power dissipation (nominal) designed for dynamic power management of core and peripherals software controlled clock gating of peripherals low power stop mode, with all clocks stopped ? fabricated in 90 nm process ? 1.2 v internal logic ? single power supply with 5.0 v ???? ? ? 5% (4.5 v to 5.25 v) with internal regulator to provide 3.3 v and 1.2 v for the core ? input and output pins with 5.0 v ???? ? ? 5% (4.5 v to 5.25 v) range 35%/65% v dde cmos switch levels (with hysteresis) selectable hysteresis selectable slew rate control ? nexus pins powered by 3.3 v supply ? designed with emi reduction techniques phase-locked loop frequency modulation of system clock frequency on-chip bypass capacitance selectable slew rate and drive strength high performance e200z335 core processor ? 32-bit power architecture book e programmer?s model ? variable length encoding enhancements allows power architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions results in smaller code size ? single issue, 32-bit power architecture technology compliant cpu ? in-order execution and retirement ? precise exception handling ? branch processing unit dedicated branch address calculation adder branch acceleration using branch lookahead instruction buffer ? load/store unit one-cycle load latency fully pipelined big and little endian support misaligned access support zero load-to-use pipeline bubbles ? thirty-two 64-bit general purpose registers (gprs)
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 13/142 ? memory management unit (mmu) with 16-entry fully-associative translation look- aside buffer (tlb) ? separate instruction bus and load/store bus ? vectored interrupt support ? interrupt latency < 120 ns @ 80 mhz (measured from interrupt request to execution of first instruction of interrupt exception handler) ? non-maskable interrupt (nmi) input for handling external events that must produce an immediate response, e.g., power down detection. on this device, the nmi input is connected to the critical interrupt input. (may not be recoverable) ? critical interrupt input. for external interrupt sources that are higher priority than provided by the interrupt controller. (always recoverable) ? new ?wait for interrupt? instruction, to be used with new low power modes ? reservation instructions for implementing read-modify-write accesses ? signal processing extension (spe) apu operating on all 32 gprs that are all extended to 64 bits wide provides a full compliment of vector and scalar integer and floating point arithmetic operations (including integer vector mac and mul operations) (simd) provides rich array of extended 64-bit loads and stores to/from extended gprs fully code compatible with e200z6 core ? floating point (fpu) ieee 754 compatible wit h software wrapper scalar single precision in hardware, double precision with software library conversion instructions between single precision floating point and fixed point fully code compatible with e200z6 core ? long cycle time instructions, except for guarded loads, do not increase interrupt latency ? extensive system development support through nexus debug port advanced microcontroller bus architecture (amba) crossbar switch (xbar) ? three master ports, four slave ports masters: cpu instruction bus; cpu load/store bus (nexus); edma slave: flash; sram; peripheral bridge; calibration ebi ? 32-bit internal address bus, 64-bit internal data bus enhanced direct memory access (edma) controller ? 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers ? supports variable sized queues and circular queues ? source and destination address registers are independently configured to post- increment or remain constant ? each transfer is initiated by a peripheral, cpu, or edma channel request ? each edma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer interrupt controller (intc) ? 191 peripheral interrupt request sources ? 8 software setable interrupt request sources
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 14/142 doc id 14642 rev 11 ?9-bit vector unique vector for each interrupt request source provided by hardware connection to processor or read from register ? each interrupt source can be programmed to one of 16 priorities ?preemption preemptive prioritized interrupt requests to processor isr at a higher priority preempts isrs or tasks at lower priorities automatic pushing or popping of preempted priority to or from a lifo ability to modify the isr or task priority . modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. ? low latency?three clocks from receipt of interrupt request from peripheral to interrupt request to processor frequency modulating phase-locked loop (fmpll) ? reference clock pre-divider (prediv) for finer frequency synthesis resolution ? reduced frequency divider (rfd) for re ducing the fmpll output clock frequency without forcing the fmpll to re-lock ? system clock divider (sysdiv) for reducing the system clock frequency in normal or bypass mode ? input clock frequency range from 4 mhz to 20 mhz before the pre-divider, and from 4 mhz to 16 mhz at the fmpll input ? voltage controlled oscillator (vco ) range from 256 mhz to 512 mhz ? vco free-running frequency range from 25 mhz to 125 mhz ? four bypass modes: crystal or external reference with pll on or off ? two normal modes: crystal or external reference ? programmable frequency modulation triangle wave modulation register programmable modulation frequency and depth ? lock detect circuitry reports when the fmpll has achieved frequency lock and continuously monitors lock status to report loss of lock conditions user-selectable ability to generate an interrupt request upon loss of lock user-selectable ability to generate a system reset upon loss of lock ? clock quality monitor (cqm) module pr ovides loss-of-clock detection for the fmpll reference and output clocks user-selectable ability to generate an interrupt request upon loss of clock user-selectable ability to generate a system reset upon loss of clock backup clock (reference clock or fmpll free-running) can be applied to the system in case of loss of clock calibration bus interface (ebi) ? available only in the calibration package (496 csp package) ? 1.8 v to 3.3 v 10% i/o (1.6 v to 3.6 v) ? memory controller with support for various memory types ? 16-bit data bus, up to 22-bit address bus ? selectable drive strength
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 15/142 ? configurable bus speed modes ?bus monitor ? configurable wait states system integration unit (siu) ? centralized gpio control of 80 i/o pins ? centralized pad control on a per-pin basis pin function selection configurable weak pull-up or pull-down drive strength slew rate hysteresis ? system reset monitoring and generation ? external interrupt inputs, filtering and control ? critical interrupt control ? non-maskable interrupt control ? internal multiplexer subblock (imux) allows flexible selection of eqadc tr igger inputs (etpu, emios and external signals) allows selection of interrupt requests between external pins and dspi error correction status module (ecsm) ? configurable error-correcting codes (ecc) reporting ? single-bit error correction reporting on-chip flash memory ? up to 1.5 mb flash memory, accessed via a 64-bit wide bus interface ? 16 kb shadow block ? fetch accelerator provide single cycle flash access at 80 mhz quadruple 128-bit wide prefetch/burst buffers prefetch buffers can be configured to prefetch code or data or both ? censorship protection scheme to prevent flash content visibility ? flash divided into two independent arrays, allowing reading from one array while erasing/programming th e other array (used for eeprom emulation) ? memory block: for spc563m64: 18 blocks (4 ?? 16 kb, 2 ?? 32 kb, 2 ?? 64 kb, 10 ?? 128 kb) for spc563m60p: 14 blocks (4 ?? 16 kb, 2 ?? 32 kb, 2 ?? 64 kb, 6 ?? 128 kb) for spc563m54p: 12 blocks (4 ?? 16 kb, 2 ?? 32 kb, 2 ?? 64 kb, 4 ?? 128 kb) ? hardware programming state machine on-chip static ram ? for spc563m64: 94 kb general purpose ram of which 32 kb are on standby power supply ? for spc563m60p: 64 kb general purpose ram of which 32 kb are on standby power supply ? for spc563m54p: 48 kb general purpose ram of which 24 kb are on standby
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 16/142 doc id 14642 rev 11 power supply boot assist module (bam) ? enables and manages the transition of mcu from reset to user code execution in the following configurations: execution from internal flash memory execution from external memory on the calibration bus download and execution of code via flexcan or esci periodic interrupt timer (pit) ? 32-bit wide down counter with automatic reload ? four channels clocked by system clock ? one channel clocked by crystal clock ? each channel can produce periodic software interrupt ? each channel can produce periodic triggers for eqadc queue triggering ? one channel out of the five can be used as wake-up timer to wake device from low power stop mode system timer module (stm) ? 32-bit up counter with 8-bit prescaler ? clocked from system clock ? four-channel timer compare hardware ? each channel can generate a unique interrupt request ? designed to address autosar task monitor function software watchdog timer (swt) ? 32-bit timer ? clock by system clock or crystal clock ? can generate either system reset or non-maskable interrupt followed by system reset ? enabled out of reset enhanced modular i/o system (emios) ? 16 timer channels (up to 14 channels in lqfp144) ? 24-bit timer resolution ? 3 selectable time bases plus shared time or angle counter bus from etpu2 ? dma and interrupt request support ? motor control capability second-generation enhanced time processor unit (etpu2) ? object-code compatible with etpu?no changes are required to hardware or software if only etpu features are used ? intelligent co-pro cessor designed for timing control ? high level tools, assembler and compiler available ? 32 channels (each channel has dedicated i/o pin in all packages except lqfp100) ? 24-bit timer resolution ? 14 kb code memory and 3 kb data memory ? double match and capture on all channels
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 17/142 ? angle clock hardware support ? shared time or angle counter bus with emios ? dma and interrupt request support ? nexus class 1 debug support ? etpu2 enhancements counters and channels can run at full system clock speed software watchdog real-time performance monitor instruction set enhancements for smaller more flexible code generation programmable channel mode for customization of channel operation enhanced queued a/d converter (eqadc) ? two independent on-chip redundant signed digit (rsd) cyclic adcs 8-, 10-, and 12-bit resolution differential conversions targets up to 10-bit accuracy at 500 ksample/s (adc_clk = 7.5 mhz) and 8-bit accuracy at 1 msample/s (adc_clk = 15 mhz) for differential conversions differential channels include variable gain amplifier (vga) for improved dynamic range ( ? 1; ? 2; ? 4) differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k ? ; 100 k ? ; low value of 5 k ? ) single-ended signal range from 0 to 5 v sample times of 2 (default), 8, 64 or 128 adc clock cycles provides time stamp information when requested parallel interface to eqadc command fifos (cfifos) and result fifos (rfifos) supports both right-justified unsigned and signed formats for conversion results temperature sensor to enable measurement of die temperature ability to measure all power supply pins directly ? automatic application of adc calibration constants provision of reference voltages (25% vref and 75% vref) for adc calibration purposes ? up to 34 (b) input channels available to the two on-chip adcs ? four pairs of differential analog input channels ? full duplex synchronous serial interface to an external device has a free-running clock for use by the external device supports a 26-bit message length transmits a null message when there are no triggered cfifos with commands bound for external cbuffers, or when there are triggered cfifos with commands bound for external cbuffers but the external cbuffers are full ? parallel side interface to communicate with an on-chip companion module ? zero jitter triggering for queue 0. (queue 0 trigger causes current conversion to be b. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 18/142 doc id 14642 rev 11 aborted and the queued conversions in the cbuffer to be bypassed. delay from trigger to start of conversion is 13 system clocks + 1 adc clock.) ? eqadc result streaming. generation of a continuous stream of adc conversion results from a single eqadc command word. controlled by two different trigger signals; one to define the rate at which results are generated and the other to define the beginning and ending of the stream. used to digitize waveforms during specific time/angle windows, e.g., engine knock sensor sampling. ? angular decimation. the ability of the eq adc to sample an analog waveform in the time domain, perform finite impulse response (fir) or infinite impulse response (iir) filtering also in the time domain, but to down sample the results in the angle domain. resulting in a time domain filtered result at a given engine angle. ? priority based cfifos supports six cfifos with fixed priority. the lower the cfifo number, the higher its priority. when commands of distinct cfifos are bound for the same cbuffer, the higher priority cfifo is always served first. supports software and several hardware trigger modes to arm a particular cfifo generates interrupt when command coherency is not achieved ? external hardware triggers supports rising edge, falling edge, high level and low level triggers supports configurable digital filter ? supports four external 8-to-1 muxes which can expand the input channel number from 34 (c) to 59 two deserial serial peripheral interface modules (dspi) ?spi full duplex communication ports with interrupt and dma request support support for queues in ram 6 chip selects, expandable to 64 with external demultiplexers programmable frame size, baud rate, clock delay and clock phase on a per frame basis modified spi mode for interfacing to peripherals with longer setup time requirements lvds option for output clock and data to allow higher speed communication ? deserial serial interface (dsi) pin reduction by hardware serialization and deserialization of etpu, emios channels and gpio 32 bits per dspi module triggered transfer control and change in data transfer control (for reduced emi) compatible with microsecond channel version 1.0 downstream c.176-pin and 208-ball packages.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 19/142 two enhanced serial communication interface (esci) modules ? uart mode provides nrz format and half or full duplex interface ? esci bit rate up to 1 mbps ? advanced error detection, and optional parity generation and detection ? word length programmable as 8, 9, 12 or 13 bits ? separately enabled transmitter and receiver ? lin support ? dma support ? interrupt request support ? programmable clock source: syst em clock or o scillator clock ? support microsecond channel (timed serial bus - tsb) upstream version 1.0 tw o f l ex c a n ? one with 32 message buffers; the second with 64 message buffers ? full implementation of the can protocol specification, version 2.0b ? programmable acceptance filters ? short latency time for high priority transmit messages ? arbitration scheme according to message id or message buffer number ? listen only mode capabilities ? programmable clock source: syst em clock or o scillator clock ? message buffers may be configured as mailboxes or as fifo nexus port controller (npc) ? per ieee-isto 5001-2003 ? real time development support for power architecture core and etpu engine through nexus class 2/1 ? read and write access (nexus class 3 feat ure that is supported on this device) run-time access of entire memory map calibration ? support for data value breakpoints / watchpoints run-time access of entire memory map calibration table constants calibrated using mmu and internal and external ram scalar constants calibrated using cache line locking ? configured via the ieee 1149.1 (jtag) port ieee 1149.1 jtag controller (jtagc) ? ieee 1149.1-2001 test access port (tap) interface ? 5-bit instruction regist er that supports ieee 1149.1-20 01 defined instructions ? 5-bit instruction register that su pports additional public instructions ? three test data registers: a bypass register, a boundary scan register, and a device identification register ? censorship disable register. by writing the 64-bit serial boot password to this register, censorship may be disabled until the next reset ? tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 20/142 doc id 14642 rev 11 on-chip voltage regulator for single 5 v supply operation ? on-chip regulator 5 v to 3.3 v for internal supplies ? on-chip regulator controller 5 v to 1.2 v (with external bypass transistor) for core logic low-power modes ? slow mode. allows device to be run at very low speed (approximately 1 mhz), with modules (including the pll) selectively disabled in software ? stop mode. system clock stopped to all modules including the cpu. wake-up timer used to restart the system clock after a predetermined time 2.3 spc563mxx feature details 2.3.1 e200z335 core the e200z335 processor utilizes a four stage pipeline for instruction execution. the instruction fetch (stage 1), instruction de code/register file r ead/effective address calculation (stage 2), execute/memory access (stage 3), and register writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmetic unit (au), a logic unit (lu), a 32- bit barrel shifter (shifter), a mask-insertion un it (miu), a condition register manipulation unit (cru), a count-leading-zeros unit (clz), a 32 ? 32 hardware multip lier array, result feed-forward hardware, and support hardware for division. most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. a count-leading-zeros unit operates in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch address adder to minimize delays during change of flow operat ions. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching is performed to accelerate taken branches. prefetched instructions are placed into an instruction buffer capable of holding six instructions. branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the instruction decode stage, allowing the branch target to be prefetched early. when a branch is detected at the instruction buffer, a prediction may be made on whether the branch is taken or not. if the branch is predicted to be taken, a target fetch is initiated and its target instructions are placed in the instruction buffer following the branch instruction. many branches take zero cycle to execute by using branch folding. branches are folded out from the instruction execution pipe whenever possible. these include unconditional branches and conditional branches with condition codes that can be resolved early. conditional branches which are not taken and not folded execute in a single clock. branches with successful target prefetching which are not folded have an effective execution time of one clock. all other taken branches have an execution time of two clocks. memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. these instructions can be pipelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load/store unit contains a dedicated effective address adder to allow effective address
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 21/142 generation to be optimized. also, a load-to-use dependency does not incur any pipeline bubbles for most cases. the condition register unit supports the condition register (cr) and condition register operations defined by the power architecture. th e condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. vectored and autovectored interrupts are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. the hardware floating-p oint unit utilizes the ieee-754 singl e-precision floati ng-point format and supports single-precision floating-point operations in a pipelined fashion. the general purpose register file is used for source and destination operands, thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type. single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. divide instructions ar e multi-cycle and are not pipelined. the signal processing extension (spe) auxiliary processing unit (apu ) provides hardware simd operations and supports a full complement of dual integer arithmetic operation including multiply accumulate (m ac) and dual integer multiply (mul) in a pipelined fashion. the general purpose register file is enhanced such that all 32 of the gprs are extended to 64 bits wide and are used for source and destination operands, thus there is a unified storage model for 32 ? 32 mac operations which generate greater than 32-bit results. the majority of both scalar and vector operations (including mac and mul) are executed in a single clock cycle. both scalar and vector di vides take multiple clocks. the spe apu also provides extended load and store operations to support the transfer of data to and from the extended 64-bit gprs. the cpu includes support for variable length encoding (vle) instruction enhancements. this enables the classic power architecture instruction set to be represented by a modified instruction set made up from a mixture of 16 - and 32-bit instructions. this results in a significantly smaller code size footprint without noticeably affecting performance. the power architecture instruction set an d vle instruction set are available concurrently. regions of the memory map are designated as ppc or vle using an additional configuration bit in each of table look-aside buffers (tlb) entries in the mmu. the cpu core is enhanced by the addition of two additional interrupt sources; non- maskable interrupt and critical interrupt. these two sources are routed directly from package pins, via edge detection logic in the siu to the cpu, bypassing completely the interrupt controller. once the edge detection logic is programmed, it cannot be disabled, except by reset. the non-maskable interrupt is, as the name suggests, completely un- maskable and when asserted will always result in the immediate execution of the respective interrupt service routine. the non-maskable interrupt is not guaranteed to be recoverable. the critical interrupt is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the cpu and is guaranteed to be recoverable (code execution may be resumed from where it stopped). the cpu core has an additional ?wait for interrupt? instruction that is used in conjunction with low power stop mode. when low power stop mode is selected, this instruction is executed to allow the system clock to be stopped. an external interrupt source or the system wake-up timer is used to restart the system clock and allow the cpu to service the interrupt.
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 22/142 doc id 14642 rev 11 2.3.2 crossbar the xbar multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access a different slave. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. the crossbar provides the following features: 3 master ports: ? e200z335 core complex instruction port ? e200z335 core complex load/store port ?edma 4 slave ports ? flash ? calibration bus ?sram ? peripheral bridge a/b (etpu2, emios, si u, dspi, esci, flexcan, eqadc, bam, decimation filter, pit, stm and swt) 32-bit internal address, 64-bit internal data paths 2.3.3 edma the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 32 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall block size. the edma module provides the following features: all data movement via dual-address transfers: read from source, write to destination programmable source and destination addresses, transfer size, plus support for enhanced addressing modes transfer control descriptor organized to support two-deep, nested transfer operations an inner data transfer loop defined by a ?minor? byte transfer count an outer data transfer loop defined by a ?major? iteration count channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel linki ng mechanism for continuous transfers ? peripheral-paced hardware requests (one per channel) support for fixed-priority and round-robin channel arbitration
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 23/142 channel completion reported via optional interrupt requests 1 interrupt per channel, optionally asserted at completion of major iteration count error termination interrupts are optionally enabled support for scatter/gather dma processing channel transfers can be suspended by a higher priority channel 2.3.4 interrupt controller the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. the intc allows interrupt request servicing from up to 191 peripheral interrupt request sources, plus 165 sources reserved for compatibility with other family members). for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interrupt requests to each other through software setable interrupt requests. these same software setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. the high priority portion is initiated by a peripheral interrupt request, but then the isr asserts a software setable interrupt request to finish the servicing in a lower priority isr. therefore these software setable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. the intc provides the following features: 356 peripheral interrupt request sources 8 software setable interrupt request sources 9-bit vector addresses unique vector for each interrupt request source hardware connection to processor or read from register each interrupt source can be programmed to one of 16 priorities preemptive prioritized interrupt requests to processor isr at a higher priority preempts executing isrs or tasks at lower priorities automatic pushing or popping of preempted priority to or from a lifo ability to modify the isr or ta sk priority to implement the priority ceiling protocol for accessing shared resources low latency?three clocks from receipt of interrupt request from peripheral to interrupt request to processor this device also includes a non-maskable in terrupt (nmi) pin that bypasses the intc and multiplexing logic.
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 24/142 doc id 14642 rev 11 2.3.5 fmpll the fmpll allows the user to generate high speed system clocks from a 4 mhz to 20 mhz crystal oscillator or external clock generator. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the pll has the following major features: input clock frequency from 4 mhz to 20 mhz voltage controlled oscillator (vco) range from 256 mhz to 512 mhz, resulting in system clock frequencies from 16 mhz to 80 mhz with granularity of 4 mhz or better reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock 3 modes of operation ? bypass mode with pll off ? bypass mode with pll running (default mode out of reset) ? pll normal mode each of the three modes may be run with a crystal oscillator or an external clock reference programmable frequency modulation ? modulation enabled/disabled through software ? triangle wave modulation up to 100 khz modulation frequency ? programmable modulation depth (0% to 2% modulation depth) ? programmable modulation frequency dependent on reference frequency lock detect circuitry reports when the pll has achieved frequency lock and continuously monitors lock status to report loss of lock conditions clock quality module ? detects the quality of the crystal clock and cause interrupt request or system reset if error is detected ? detects the quality of the pll output clock. if an error is detected, causes a system reset or switches the system clock to the crystal clock and causes an interrupt request programmable interrupt request or system reset on loss of lock 2.3.6 calibration ebi the calibration ebi controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. the calibration ebi is only available in the calib ration tool. the calibration ebi includes a memory controller that generates interface signals to support a variety of external memories. the calibration ebi memory controller supports legacy flash, sram, and asynchronous memories. in addition, the calibration ebi supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed region-specific attributes. the calibration ebi supports the following features: 22-bit address bus (two most significant signals multiplexed with two chip selects) 16-bit data bus multiplexed mode with addresses and data signals present on the data lines
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 25/142 note: the calibration ebi must be configured in multiplexed mode when the extended nexus trace is used on the calibration tool. this is because nexus signals and address lines of the calibration bus share the same balls in the calibration package. memory controller with support for various memory types: ? asynchronous/legacy flash and sram bus monitor ? user selectable ? programmable timeout period (with 8 external bus clock resolution) configurable wait states (via chip selects) 3 chip-select (cal_cs [0], cal_cs [2:3]) signals (multiplexed with 2 most significant address signals) 2 write/byte enable (we[0:1]/be[0:1]) signals configurable bus speed modes ? system frequency ? 1/2 of system frequency ? 1/4 of system frequency optional automatic clkout gating to save power and reduce emi selectable drive strengths; 10 pf, 20 pf, 30 pf, 50 pf 2.3.7 siu the spc563mxx siu controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the reset controller performs reset monitoring of internal and external reset sources, and drives the rstout pin. communication between the siu and the e200z335 cpu core is via the crossbar switch. the siu provides the following features: system configuration ? mcu reset configuration via external pins ? pad configuration control for each pad ? pad configuration control for virtual i/o via dspi serialization system reset monitoring and generation ? power-on reset support ? reset status register provides last reset source to software ? glitch detection on reset input ? software controlled reset assertion external interrupt ? 11 interrupt requests ? rising or falling edge event detection ? programmable digital filter for glitch rejection ? critical interrupt request ? non-maskable interrupt request
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 26/142 doc id 14642 rev 11 gpio ? gpio function on 80 i/o pins ? virtual gpio on 64 i/o pins via dspi serialization (requires external deserialization device) ? dedicated input and output registers for setting each gpio and virtual gpio pin internal multiplexing ? allows serial and parallel chaining of dspis ? allows flexible selection of eqadc trigger inputs ? allows selection of interrupt requests between external pins and dspi 2.3.8 ecsm the error correction status module provides status information regarding platform memory errors reported by error-correcting codes. 2.3.9 flash devices in the spc563mxx family provide up to 1.5 mb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used for instruction and/or data storage. the flash module includes a fetch accelerator, that optimizes the performance of the flash array to match the cpu architecture and provides single cycle random access to the flash @ 80 mhz. the flash module interfaces the system bus to a dedicated flash memory array controller. for cpu ?loads?, dma transfers and cpu instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential lines of data from the flash array into the buffer. prefetch buffer hits allow no-wait responses. normal flash array accesses are registered and are forwarded to the system bus on the following cycle, incurrin g three wait-states. prefetch operations may be automatically controlled, and are restricted to instruction fetch. the flash memory provides the following features: supports a 64-bit data bus for instructio n fetch, cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword writes are supported. fetch accelerator ? architected to optimize the performance of the flash with the cpu to provide single cycle random access to the flash up to 80 mhz system clock speed ? configurable read buffering and line prefetch support ? four line read buffers (128 bits wide) and a prefetch controller hardware and software configurable read and write access protections on a per-master basis interface to the flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs configurable access timing allowing use in a wide range of system frequencies multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation of other memory types
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 27/142 software programmable block program/erase restriction control erase of selected block(s) read page size of 128 bits (four words) ecc with single-bit correction, double-bit detection program page size of 64 bits (two words) ecc single-bit error corrections are visible to software minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ecc embedded hardware program and erase algorithm erase suspend shadow information stored in non-volatile shadow block independent program/erase of the shadow block 2.3.10 sram the spc563mxx sram module provides a general-purpose up to 94 kb memory block. the sram controller includes these features: supports read/write accesses mapped to the sram memory from any master 32 kb or 24 kb block powered by separate supply for standby operation byte, halfword, word and doubleword addressable ecc performs single-bit correction, double-bit detection on 32-bit data element 2.3.11 bam the bam (boot assist module) is a block of read-only memory that is programmed once by st and is identical for all spc563mxx mcus. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam supports different modes of booting. they are: booting from internal flash memory serial boot loading (a program is downloaded into ram via esci or the flexcan and then executed) booting from external memory on calibration bus the bam also reads the reset configuration half word (rchw) from internal flash memory and configures the spc563mxx hardware accordingly. the bam provides the following features: sets up mmu to cover all resources and mapping all physical address to logical addresses with minimum address translation sets up the mmu to allow user boot code to execute as either power architecture code (default) or as vle code detection of user boot code automatic switch to serial boot mode if internal flash is blank or invalid supports user programmable 64-bit password protection for serial boot mode supports serial bootloading via flexcan bus and esci using fixed baudrate protocol supports serial bootloading via flexcan bus and esci with auto baud rate sensing supports serial bootloading of either power architecture code (default) or vle code
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 28/142 doc id 14642 rev 11 supports booting from calibration bus interface supports censorship protection for internal flash memory provides an option to enable the core watchdog timer provides an option to disable the software watchdog timer 2.3.12 emios the emios (enhanced modular input output system) module provides the functionality to generate or measuretime events. the channels on this module provide a range of operating modes including the capability to perform dual input capture or dual output compare as well as pwm output. the emios provides the following features: 16 channels (24-bit timer resolution) for compatibility with other family member s selected channels and timebases are implemented: ? channels 0 to 6, 8 to 15, and 23 ? timebases a, b and c channels 1, 3, 5 and 6 support modes: ? general purpose input/output (gpio) ? single action input capture (saic) ? single action output compare (saoc) channels 2, 4, 11 and 13 support all the modes above plus: ? output pulse width modulation buffered (opwmb) channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus: ? input period measurement (ipm) ? input pulse width measurement (ipwm) ? double action output compare (set flag on both matches) (daoc) ? modulus counter buffered (mcb) ? output pulse width and frequency modulation buffered (opwfmb) three 24-bit wide counter buses ? counter bus a can be driven by channel 23 or by the etpu2 and all channels can use it as a reference ? counter bus b is driven by channel 0 and channels 0 to 6 can use it as a reference ? counter bus c is driven by channel 8 and channels 8 to 15 can use it as a reference shared time bases with the etpu2 through the counter buses synchronization among internal and external time bases 2.3.13 etpu2 the etpu2 is an enhanced co-processor designed for timing control. operating in parallel with the host cpu, etpu2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. consequently, for each timer event, the host cpu setup and service times are minimized or eliminated. a powerful timer subsystem is formed by combining the etpu2 with its own
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 29/142 instruction and data ram. high-level asse mbler/compiler and do cumentation allows customers to develop their own functions on the etpu2. the etpu2 includes these distinctive features: the timer counter (tcr1), channel logic and digital filters (both channel and the external timer clock input [tcrclk]) now have an option to run at full system clock speed or system clock / 2. channels support unordered transitions: transition 2 can now be detected before transition 1. related to this enhancement, the transition detection latches (tdl1 and tdl2) can now be independently negated by microcode. a new user programmable channel mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. microinstructions now provide an option to issue interrupt and data transfer requests selected by channel. they can also be requested simultaneously at the same instruction. channel flags 0 and 1 can now be tested for branching, in addition to selecting the entry point. channel digital filters can be bypassed. the timer counter (tcr1), channel logic and digital filters (both channel and the external timer clock input [tcrclk]) now have an option to run at full system clock speed or system clock / 2. channels support unordered transitions: transition 2 can now be detected before transition 1. related to this enhancement, the transition detection latches (tdl1 and tdl2) can now be independently negated by microcode. a new user programmable channel mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. microinstructions now provide an option to issue interrupt and data transfer requests selected by channel. they can also be requested simultaneously at the same instruction. channel flags 0 and 1 can now be tested for branching, in addition to selecting the entry point. channel digital filters can be bypassed. 32 channels, each channel is associated with one input and one output signal ? enhanced input digital filters on the input pins for improved noise immunity. ? identical, orthogonal channels: each channel can perform any time function. each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. ? each channel has an event mechanism which supports single and double action functionality in various combinations. it includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators ? input and output signal states visible from the host
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 30/142 doc id 14642 rev 11 2 independent 24-bit time bases for channel synchronization: ? first time base clocked by system clock with programmable pre scale division from 2 to 512 (in steps of 2), or by output of second time base prescaler ? second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time ? both time bases can be exported to the emios timer module ? both time bases visible from the host event-triggered microengine: ? fixed-length instruction execution in two-system-clock microcycle ? 14 kb of code memory (scm) ? 3 kb of parameter (data) ram (spram) ? parallel execution of data memory, alu, channel control and flow control sub- instructions in se lected combinations ? 32-bit microengine registers and 24-bit wide alu, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution ? additional 24-bit multiply /mac/divide unit which supports all signed/unsigned multiply/mac combinations , and unsigned 24-bit divide. the mac/divide unit works in parallel with the regular microcode commands resource sharing features support channel use of common channel registers, memory and microengine time: ? hardware scheduler works as a ?task management? unit, dispatching event service routines by predefined, host-configured priority ? automatic channel context switch when a ?task switch? occurs, i.e., one function thread ends and another begins to servic e a request from other channel: channel- specific registers, flags and parameter base address are automatically loaded for the next serviced channel ? spram shared between host cpu and etpu2, supporting communication either between channels and host or inter-channel ? dual-parameter coherency hardware support allows atomic access to two parameters by host test and development support features: ? nexus class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions ? software breakpoints ? scm continuous signature-check built-i n self test (misc ? multiple input signature calculator), runs concurrently with etpu2 normal operation system enhancements ? software watchdog with programmable timeout ? real-time performance information channel enhancements ? channels 1 and 2 can optionally drive angle clock hardware programming enhancements ? engine relative addressing mode
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 31/142 2.3.14 eqadc the enhanced queued analog to digital converter (eqadc) block provides accurate and fast conversions for a wide range of applications. the eqadc provides a parallel interface to two on-chip analog to digital converters (adc), and a single master to single slave serial interface to an off-chip external device. both on-chip adcs have access to all the analog channels. the eqadc prioritizes and transfers commands from six command conversion command ?queues? to the on-chip adcs or to the external device. the block can also receive data from the on-chip adcs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. the six command queues are prioritized with queue_0 having the highest priority and queue_5 the lowest. queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either adc and start a queue_0 conv ersion. this means that queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the adcs were performing when the trigger occurred. the eqadc supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip adcs or to the external device. it also monitors the fullness of command queues and result queues, and accordingly generates dma or interrupt requests to control data movement between the queues and the system memory, which is external to the eqadc. the adcs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. these features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. the eqadc also integrates a programmable decimation filter capable of taking in adc conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result fifos. this allows the adcs to sample the sens or at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount dsp processing bandwidth required to fully process the digitized waveform. the eqadc provides the following features: dual on-chip adcs ?2 ? 12-bit adc resolution ? programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit) 12-bit conversion time ? 1 ? s (1m sample/sec) 10-bit conversion time ? 867 ns (1.2m sample/second) 8-bit conversion time ? 733 ns (1.4m sample/second) ? up to 10-bit accuracy at 500 ksample/s and 9-bit accuracy at 1 msample/s ? differential conversions ? single-ended signal range from 0 to 5 v ? variable gain amplifiers on differential inputs ( ? 1, ? 2, ? 4) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles ? provides time stamp information when requested ? parallel interface to eqadc cfifos and rfifos ? supports both right-justified unsigned and signed formats for conversion results
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 32/142 doc id 14642 rev 11 up to 34 (d) input channels (accessible by both adcs) 23 additional internal channels for measuring control and monitoring voltages inside the device ? including core voltage, i/o voltage, lvi voltages, etc. an internal bandgap reference to allow absolute voltage measurements 4 pairs of differential analog input channels ? programmable pull-up/pull-down resistors on each differential input for biasing and sensor diagnostic (200 k ? , 100 k ? , 5 k ? ) silicon die temperature sensor ? provides temperature of s ilicon as an analog value ? read using an internal adc analog channel ? may be read with either adc decimation filter ? programmable decimation factor (2 to 16) ? selectable iir or fir filter ? up to 4th order iir or 8th order fir ? programmable coefficients ? saturated or non-saturated modes ? programmable rounding (convergent; two?s complement; truncated) ? pre-fill mode to pre-cond ition the filter before the sample window opens full duplex synchronous serial interface to an external device ? free-running clock for use by an external device ? supports a 26-bit message length priority based queues ? supports six queues with fixed priority. when commands of distinct queues are bound for the same adc, the higher priority queue is always served first ? queue_0 can bypass all prioritization, buffering and abort current conversions to start a queue_0 conversion a deterministic time after the queue trigger ? streaming mode operation of queue_0 to execute some commands several times ? supports software and hardware trigger modes to arm a particular queue ? generates interrupt when command coherency is not achieved external hardware triggers ? supports rising edge, falling edge, high level and low level triggers ? supports configurable digital filter supports four external 8-to-1 muxes which can expand the input channels to 56 channels total 2.3.15 dspi the deserial serial peripheral interface (dspi) block provides a synchronous serial interface for communication between the spc563mxx mcu and external devices. the dspi supports d. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 33/142 pin count reduction through serialization and deserialization of etpu and emios channels and memory-mapped registers. the channels and register content are transmitted using a spi-like protocol. this spi-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. each bit in the frame may be configured to serialize either etpu channels, emios channels or gpio signals. the dspi can be configured to serialize data to an external device that supports the microsecond channel protocol. there are two identical dspi blocks on the spc563mxx mcu. the dspi output pins support 5 v logic levels or low voltage differential signalling (lvd s) according to the microsecond channel specification. the dspis have three configurations: serial peripheral interface (spi) configuration where the dspi operates as an up to 16- bit spi with support for queues enhanced deserial serial interface (dsi) configuration where dspi serializes up to 32 bits with three possible sources per bit ? etpu, emios, new virtual gpio registers as possible bit source ? programmable inter-frame gap in continuous mode ? bit source selection allows microsecond channel downstream with command or data frames up to 32 bits ? microsecond channel dual receiver mode combined serial interface (csi) configuration where the dspi operates in both spi and dsi configurations interleaving dsi frames with spi frames, giving priority to spi frames for queued operations, the spi queues reside in system memo ry external to the dspi. data transfers between the memory and the dspi fifos are accomplished through the use of the edma controller or through host software. the dspi supports these spi features: full-duplex, synchronous transfers selectable lvds pads working at 40 mhz for sout and sck pins master and slave mode buffered transmit operation using the tx fifo with parameterized depth of 4 entries buffered receive operation using the rx fifo with parameterized depth of 4 entries tx and rx fifos can be disabled individually for low-latency updates to spi queues visibility into the tx and rx fifos for ease of debugging fifo bypass mode for low-latency updates to spi queues programmable transfer attributes on a per-frame basis: ? parameterized number of transfer attribute registers (from two to eight) ? serial clock with programmable polarity and phase ? various programmable delays: pcs to sck delay sck to pcs delay delay between frames ? programmable serial frame size of 4 to 16 bits, expandable with software control ? continuously held ch ip select capability
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 34/142 doc id 14642 rev 11 6 peripheral chip selects, expandable to 64 with external demultiplexer deglitching support for up to 32 peripheral chip selects with ex ternal demultiplexer dma support for adding entries to tx fifo and removing entries from rx fifo: ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) 6 interrupt conditions: ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) ? attempt to transmit with an empty transmit fifo (tfuf) ? rx fifo is not empty (rfdf) ? fifo underrun (slave only and spi mode, the slave is asked to transfer data when the txfifo is empty) ? fifo overrun (serial frame re ceived while rx fifo is full) modified transfer formats for communication with slower peripheral devices continuous serial communications clock (sck) power savings via support for stop mode enhanced dsi logic to implement a 32-bit timed serial bus (tsb) configuration, supporting the microsecond channel downstream frame format the dspis also support these features unique to the dsi and csi configurations: 2 sources of the serialized data: ? etpu_a and emios output channels ? memory-mapped register in the dspi destinations for the deserialized data: ? etpu_a and emios input channels ? siu external interrupt request inputs ? memory-mapped register in the dspi deserialized data is provided as parallel output signals and as bits in a memory- mapped register transfer initiation conditions: ? continuous ? edge sensitive hardware trigger ? change in data pin serialization/deserialization with interleaved spi frames for control and diagnostics continuous serial communications clock support for parallel and serial chaining of up to four dspi blocks 2.3.16 esci the enhanced serial communications interfac e (esci) allows asynchronous serial communications with peripheral devices and othe r mcus. it includes special support to
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 35/142 interface to local interconnect network (lin) slave devices. the esci block provides the following features: full-duplex operation standard mark/space non-return-to-zero (nrz) format 13-bit baud rate selection programmable 8-bit or 9-bit, data format programmable 12-bit or 13-bit data format for timed serial bus (tsb) configuration to support the microsecond channel upstream automatic parity generation lin support ? autonomous transmission of entire frames ? configurable to support all revisions of the lin standard ? automatic parity bit generation ? double stop bit after bit error ? 10- or 13-bit break support separately enabled transmitter and receiver programmable transmitter output parity 2 receiver wake up methods: ? idle line wake-up ? address mark wake-up interrupt-driven operation with flags receiver framing error detection hardware parity checking 1/16 bit-time noise detection dma support for both transmit and receive data ? global error bit stored with receive data in system ram to allow post processing of errors 2.3.17 flexcan the spc563mxx mcu contains two controller area network (flexcan) blocks. the flexcan module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protoc ol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. flexcan module ?a? contains 64 message buffers (mb); flexcan module ?c? contains 32 message buffers.
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 36/142 doc id 14642 rev 11 the flexcan module provides the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/s content-related addressing 64 / 32 message buffers of zero to eight bytes data length individual rx mask register per message buffer each message buffer configurable as rx or tx, all supporting standard and extended messages includes 1056 / 544 bytes of embedded memory for message buffer storage includes a 256-byte and a 128-byte memories for storing individual rx mask registers full featured rx fifo with storage capacity for six frames and internal pointer handling powerful rx fifo id filtering, capable of matching incoming ids against 8 extended, 16 standard or 32 partial (8 bits) id s, with individual masking capability selectable backwards compatibilit y with previous flexcan versions programmable clock source to the can protocol interface, either system clock or oscillator clock listen only mode capability programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id, lowest buffer number or highest priority time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts warning interrupts when the rx and tx error counters reach 96 independent of the transmission medium (an external transceiver is assumed) multi master concept high immunity to emi short latency time due to an arbitration scheme for high-priority messages low power mode, with programmable wake-up on bus activity 2.3.18 system timers the system timers provide two di stinct types of system timer: periodic interrupts/triggers using the periodic interrupt timer (pit) operating system task monitors using the system timer module (stm) periodic interrupt timer (pit) the pit provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. the pit has no external input or output pins and is intended to be used to provide system ?tick? signals to the op erating system, as well as periodic triggers for eqadc queues. of the five channels in the pit, four are clocked by the system clock, one is
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 37/142 clocked by the crystal clock. this one channel is also referred to as real time interrupt (rti) and is used to wakeup the device from low power stop mode. the following features are implemented in the pit: 5 independent timer channels each channel includes 32-bit wide down counter with automatic reload 4 channels clocked from system clock 1 channel clocked from crystal clock (wake-up timer) wake-up timer remains active when system stop mode is entered. used to restart system clock after predefined timeout period each channel can optionally generate an interrupt request or a trigger event (to trigger eqadc queues) when the timer reaches zero system timer module (stm) the system timer module (stm) is designed to implement the software task monitor as defined by autosar (see http://www.autosar.org ). it consists of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. these comparators produce a cpu interrupt when the timer exceeds the programmed value. the following features are implemented in the stm: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 2.3.19 software watchdog timer (swt) the software watchdog timer (swt) is a second watchdog module to complement the standard power architecture watchdog integrated in the cpu core. the swt is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. the following features are implemented: 32-bit modulus counter clocked by system clock or crystal clock optional programmable watchdog window mode can optionally cause system reset or interrupt request on timeout reset by writing a software key to memory mapped register enabled out of reset configuration is protected by a software key or a write-once register 2.3.20 debug features nexus port controller the npc (nexus port controller) block provid es real-time developmen t support capabilities for the spc563mxx power architecture-based mcu in compliance with the ieee-isto 5001-2003 standard. this development support is supplied for mcus without requiring
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 38/142 doc id 14642 rev 11 external address and data pins for internal visibility. the npc block is an integration of several individual nexus blocks that are selected to provide the development support interface for spc563mxx. the npc block interf aces to the host processor (e200z335), etpu, and internal buses to provide developm ent support as per t he ieee-isto 5001-2003 standard. the development support provided includes program trace and run-time access to the mcus internal memory map and access to the power architecture and etpu internal registers during halt. the nexus interface also supports a jtag only mode using only the jtag pins. spc563mxx in the production lqfp144 supports a 3.3 v reduced (4-bit wide) auxiliary port. these nexus port pins can also be used as 5 v i/o sig nals to increase usable i/o count of the device. when using this nexus port as io, nexus trace is still possible using calibration tool calibration. in the calibration tool calibration pac kage, the full 12-bit auxiliary port is available. note: in the calibration tool package, the full nexu s auxiliary port shares balls with the addresses of the calibration bus. therefore multiplexed address/data bus mode must be used for the calibration bus when using full width nexu s trace in calibration tool assembly. the following features are implemented: 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) ? always available in production package ? supports both jtag boundary scan and debug modes ?3.3v interface ? supports nexus class 1 features ? supports nexus class 3 read/write feature 9-pin reduced port interface in lqfp144 production package ? alternate function as io ? 5 v (in gpio or alternate function mode), 3.3 v (in nexus mode) interface ? auxiliary output port 1 mcko (message clock out) pin 4 mdo (message data out) pins 2 mseo (message start/end out) pins 1 evto (event out) pin ? auxiliary input port 1 evti (event in) pin 17-pin full port interface in calibration package used on calibration tool boards ?3.3v interface ? auxiliary output port 1 mcko (message clock out) pin 4 (reduced port mode) or 12 (full port mode) mdo (message data out) pins; 8 extra full port pins shared with calibration bus 2 mseo (message start/end out) pins 1 evto (event out) pin ? auxiliary input port 1 evti (event in) pin
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 39/142 host processor (e200) development support features ? ieee-isto 5001-2003 st andard class 2 compliant ? program trace via branch trace messaging (btm). branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, static code may be traced. ? watchpoint trigger enable of program trace messaging ? data value breakpoints (jtag feature of the e200z335 core): allows cpu to be halted when the cpu writes a specific value to a memory location 4 data value breakpoints cpu only detects ?equal? and ?not equal? byte, half word, word (naturally aligned) note: this feature is imprec ise due to cpu pipelining. ? subset of power architecture software debug facilities with once block (nexus class 1 features) etpu development support features ? ieee-isto 5001-2003 standard cl ass 1 compliant for the etpu ? nexus based breakpoint configuration and single step support (jtag feature of the etpu) run-time access to the on-chip memory map via the nexus read/write access protocol. this feature supports accesses for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems. all features are indep endently configurable and contro llable via the ieee 1149.1 i/o port power-on-reset status indication during reset via mdo[0] in disabled and reset modes jtag the jtagc (jtag controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee 1149.1-2001 standard and su pports the following features: ieee 1149.1-2001 test access port (tap) interface 4 pins (tdi, tms, tck, and tdo) a 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass, idcode, extest, sample, sample/preload, highz, clamp a 5-bit instruction register that supports the additional followin g public instructions: ? access_aux_tap_npc ? access_aux_tap_once ? access_aux_tap_etpu ? access_censor
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 40/142 doc id 14642 rev 11 3 test data registers to support jtag boundary scan mode ? bypass register ? boundary scan register ? device identification register a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry censorship inhibit register ? 64-bit censorship password register ? if the external tool writes a 64-bit password that matches the serial boot password stored in the internal flash shadow row, censorship is disabled until the next system reset. 2.4 spc563mxx series architecture 2.4.1 block diagram figure 1 shows a top-level block diagram of the spc563mxx series.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p overview doc id 14642 rev 11 41/142 figure 1. spc563mxx series block diagram 2.4.2 block summary ta bl e 3 summarizes the functions of the bloc ks present on the spc563mxx series microcontrollers. pll nexus 2+ mmu nexus sram siu calibration interface edma reset control 62 kb interrupt external imux gpio & engine jtag nexus ram 14 kb/3 kb 2x adci etpu crossbar switch pad control jtag port nexus port analog v stby e200z335 interrupt blocks & edma 64-bit spe 16 ch. dspis emios controller 2x cans 32 ch.+ amux adc bus 3 x 4 bam 32 kb s m m s eqadc nexus 1 peripheral bridge peripheral requests from interrupt request interrupt request edma, flash, bridge b, crossbar, sram configuration etpu i/o clocks serial analog if dma requests from peripheral blocks m instructions data s voltage regulator (1.2v, 3.3v, stb ram) nmi swt pit critical stm nmi siu escis 2x . . . . . . . . . . . . (intc) adc decimation filter cqm temp. sensor 1.5 mb flash s table 3. spc563mxx series block summary block function e200z3 core executes programs and interrupt handlers. flash memory provides storage for program code, constants, and variables ram (random-access memory) provides storage for program code, constants, and variables
overview spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 42/142 doc id 14642 rev 11 calibration bus transfers data across the crossbar switch to/from peripherals attached to the vertical connector dma (direct memory access) performs complex data movements with minimal intervention from the core dspi (deserial serial peripheral interface) provides a synchronous serial interface for communication with external devices emios (enhanced modular input-output system) provides the functionality to generate or measure events eqadc (enhanced queued analog-to-digital converter) provides accurate and fast conversions for a wide range of applications esci (serial communication interface) allows asynchronous serial communications with peripheral devices and other microcontroller units etpu (enhanced time processor unit) processes real-time input events, performs output waveform generation, and accesses shared data without host intervention flexcan (controller area network) supports the standard can communications protocol fmpll (frequency-modu lated phase-locked loop) generates high-speed system clocks and supports the programmable frequency modulation of these clocks intc (interrupt controller) provides priority- based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparen t to system logic wh en not in test mode npc (nexus port controller) provides real-time development support capabilities in compliance with the ieee-isto 5001-2003 standard pit (peripheral interrupt timer) produces periodic interrupts and triggers temperature sensor provides the temperature of the device as an analog value swt (software watchdog timer) provides protection from runaway code stm (system timer module) timer providing a set of output compare events to support autosar and operating system tasks table 3. spc563mxx series block summary (continued) block function
spc563m64l5, spc563m64l7, spc563m60l5p, spc 563m60l7p pinout and signal description doc id 14642 rev 11 43/142 3 pinout and signal description this section contains the pinouts for all production packages for the spc563mxx family of devices. please note the following: pins labeled ?nc? are to be left unconnecte d. any connection to an external circuit or voltage may cause unpredictable device behavior or damage. pins labeled ?nic? have no internal connection. 3.1 lqfp100 pinout figure 2 shows the pinout for the 100-pin lqfp.
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 44/142 doc id 14642 rev 11 figure 2. 100-pin lqfp pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 an[11] / anz an[9] / anx vdda vssa an[39] / an[10] / any an[38] / an[8] / anw vddreg vrcctl vstby vrc33 etpu_a[31] / dspi_c_pcs[4] / etpu_a[13] / gpio[145] etpu_a[30] / dspi_c_pcs[3] / etpu_a[11] / gpio[144] etpu_a[29] / dspi_c_pcs[2] / gpio[143] etpu_a[28] / dspi_c_pcs[1] / gpio[142] (see signal details, pin 15 etpu_a[26] / irq [14] / dspi_c_sout_lvds? / gpio[140] etpu_a[25] / irq [13] / dspi_c_sck_lvds+ / gpio[139] etpu_a[24] / irq [12] / dspi_c_sck_lvds? / gpio[138] vss vddeh1a vdd etpu_a[15] / dspi_b_pcs[5] / gpio[129] vddeh1b etpu_a[14] / dspi_b_pcs[4] / etpu_a[9] / gpio[128] vss tms tdi / emios[5] / gpio[232] tck vss vddeh7 tdo / emios[6] / gpio[228] jcomp dspi_b_pcs[3] / dspi_c_sin / gpio[108] dspi_b_sin / dspi_c_pcs[2] / gpio[103] vddeh6b vss dspi_b_sck / dspi_c_pcs[1] / gpio[102] dspi_b_pcs[4] / dspi_c_sck / gpio[109] vdd rstout can_c_tx / gpio[87] can_c_rx / gpio[88] reset vss vddeh6a vsspll xtal extal / extclk vddpll vss etpu_a[13] / dspi_b_pcs[3] / gpio[127] etpu_a[8] / etpu_a[20] / dspi_b_sout_lvds+ / gpio[122] etpu_a[7] / etpu_a[19] / dspi_b_sout_lvds? / etpu_a[6] / gpio[121] etpu_a[6] / etpu_a[18] / dspi_b_sck_lvds+ / gpio[120] etpu_a[5] / etpu_a[17] / dspi_b_sck_lvds? / gpio[119] vddeh1b etpu_a[4] / etpu_a[16] / gpio[118] vss etpu_a[3] / etpu_a[15] / gpio[117] etpu_a[2] / etpu_a[14] / gpio[116] etpu_a[1] / etpu_a[13] / gpio[115] etpu_a[0] / etpu_a[12] / etpu_a[19] / gpio[114] vdd emios[0] / etpu_a[0] / etpu_a[25] / gpio[179] emios[8] / etpu_a[8] / sci_b_tx / gpio[187] emios[9] / etpu_a[9] / sci_b_rx / gpio[188] vss vddeh6a emios[12] / dspi_c_sout / etpu_a[27] / gpio[191] emios[14] / irq [0] / etpu_a[29] / gpio[193] can_a_tx / sci_a_tx / gpio[83] can_a_rx / sci_a_rx / gpio[84] pllref / irq [4]/etrig[2] / gpio[208] bootcfg1 / irq [3] / etrig[3] / gpio[212] wkpcfg / nmi / dspi_b_sout / gpio[213] an[21] an[0] (dan0+) an[1] (dan0?) an[2] (dan1+) an[3] (dan1?) an[4] (dan2+) an[5] (dan2?) an[6] (dan3+) an[7] (dan3?) refbypc vrh vrl an[23] an[25] an[28] an[31] an[33] an[35] vdd an[12] / ma[0] / etpu_a[19] / sds an[13] / ma[1] / etpu_a[21] / sdo an[14] / ma[2] / etpu_a[27] / sdi an[15] / fck / etpu_a[29] vss vddeh7 100?pin lqfp signal details: pin 15: etpu_a[27] / irq[15] / dspi_c_sout_lvds+ / dspi_b_sout / gpio[141]
spc563m64l5, spc563m64l7, spc563m60l5p, spc 563m60l7p pinout and signal description doc id 14642 rev 11 45/142 3.2 lqfp144 pinout figure 3 shows the pinout for the 144-pin lqfp. figure 3. 144-pin lqfp pinout (top view; all 144-pin devices) 144-pin lqfp 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 etpu_a[13] / dspi_b_pcs[3] / gpio[127] etpu_a[12] / dspi_b_pcs[1] / gpio[126] etpu_a[11] / etpu_a[23] / gpio[125] etpu_a[10] / etpu_a[22] / gpio[124] etpu_a[9] / etpu_a[21] / gpio[123] etpu_a[8] / etpu_a[20] / dspi_b_sout_lvds+ / gpio[122] etpu_a[7] / etpu_a[19] / dspi_b_sout_lvds? / etpu_a[6] / gpio[121] etpu_a[6] / etpu_a[18] / dspi_b_sck_lvds+ / gpio[120] etpu_a[5] / etpu_a[17] / dspi_b_sck_lvds? / gpio[119] vddeh1b etpu_a[4] / etpu_a[16] / gpio[118] vss etpu_a[3] / etpu_a[15] / gpio[117] etpu_a[2] / etpu_a[14] / gpio[116] etpu_a[1] / etpu_a[13] / gpio[115] etpu_a[0] / etpu_a[12] / etpu_a[19] / gpio[114] vdd emios[0] / etpu_a[0] / etpu_a[25] / gpio[179] emios[2] / etpu_a[2] / gpio[181] emios[4] / etpu_a[4] / gpio[183] emios[8] / etpu_a[8] / sci_b_tx / gpio[187] emios[9] / etpu_a[9] / sci_b_rx / gpio[188] vss emios[10] / gpio[189] vddeh6a emios[11] / gpio[190] emios[12] / dspi_c_sout / etpu_a[27] / gpio[191] emios[14] / irq [0] / etpu_a[29] / gpio[193] emios[23] / gpio[202] can_a_tx / sci_a_tx / gpio[83] can_a_rx / sci_a_rx / gpio[84] pllref / irq [4]/etrig[2] / gpio[208] sci_b_rx / gpio[92] bootcfg1 / irq [3] / etrig[3] / gpio[212] wkpcfg / nmi / dspi_b_sout / gpio[213] sci_b_tx / gpio[91] an[21] an[0] (dan0+) an[1] (dan0?) an[2] (dan1+) an[3] (dan1?) an[4] (dan2+) an[5] (dan2?) an[6] (dan3+) an[7] (dan3?) refbypc vrh vrl an[22] an[23] an[24] an[25] an[27] an[28] an[30] an[31] an[32] an[33] an[34] an[35] vdd an[12] / ma[0] / etpu_a[19] / sds an[13] / ma[1] / etpu_a[21] / sdo an[14] / ma[2] / etpu_a[27] / sdi an[15] / fck / etpu_a[29] vss mdo[3] / etpu_a[25] / gpio[223] vddeh7 mdo[2] / etpu_a[21] / gpio[222] mdo[1] / etpu_a[19] / gpio[221] mdo[0] / etpu_a[13] / gpio[220] mseo [0] / etpu_a[27] / gpio[224] an[18] an[17] an[16] an[11] / anz an[9] / anx vdda vssa an[39] / an[10] / any an[38] / an[8] / anw vddreg vrcctl vstby vrc33 (see signal details, pin 14) (see signal details, pin 15) etpu_a[29] / dspi_c_pcs[2] / gpio[143] etpu_a[28] / dspi_c_pcs[1] / gpio[142] (see signal details, pin 18) (see signal details, pin 19) (see signal details, pin 20) (see signal details, pin 21) vss (see signal details, pin 23) vddeh1a (see signal details, pin 25) vdd etpu_a[21] / irq [9] / gpio[135] etpu_a[20] / irq [8] / gpio[134] etpu_a[19] / gpio[133] etpu_a[18] / gpio[132] etpu_a[17] / gpio[131] etpu_a[16] / gpio[130] etpu_a[15] / dspi_b_pcs[5] / gpio[129] vddeh1b (see signal details, pin 35) vss tms tdi / emios[5] / gpio[232] evto / etpu_a[4] / gpio[227] tck vss evti / etpu_a[2] / gpio[231] vddeh7 mseo [1] / etpu_a[29] / gpio[225] tdo / emios[6] / gpio[228] mcko / gpio[219] jcomp dspi_b_pcs[3] / dspi_c_sin / gpio[108] dspi_b_sout / dspi_c_pcs[5] / gpio[104] dspi_b_sin / dspi_c_pcs[2] / gpio[103] dspi_b_pcs[0] / gpio[105] vddeh6b dspi_b_pcs[1] / gpio[106] vss dspi_b_pcs[2] / dspi_c_sout / gpio[107] dspi_b_sck / dspi_c_pcs[1] / gpio[102] dspi_b_pcs[4] / dspi_c_sck / gpio[109] dspi_b_pcs[5] / dspi_c_pcs[0] / gpio[110] vdd rstout can_c_tx / gpio[87] sci_a_tx / emios[13] / gpio[89] sci_a_rx / emios[15] / gpio[90] can_c_rx / gpio[88] reset vss vddeh6a vsspll xtal extal / extclk vddpll vss 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 signal details: pin 14: etpu_a[31] / dspi_c_pcs[4] / etpu_a[13] / gpio[145] pin 15: etpu_a[30] / dspi_c_pcs[3] / etpu_a[11] / gpio[144] pin 18: etpu_a[27] / irq [15] / dspi_c_sout_lvds+ / dspi_b_sout / gpio[141] pin 19: etpu_a[26] / irq [14] / dspi_c_sout_lvds? / gpio[140] pin 20: etpu_a[25] / irq[13] / sck_c_lvds+ / gpio[139] pin 21: etpu_a[24] / irq[12] / sck_c_lvds? / gpio[138] pin 23: etpu_a[23] / irq[11] / etpu_a[21] / gpio[137] pin 25: etpu_a[22] / irq [10] / etpu_a[17] / gpio[136] pin 35: etpu_a[14] / dspi_b_pcs[4] / etpu_a[9] / gpio[128]
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 46/142 doc id 14642 rev 11 3.3 lqfp176 pinout (spc563m64) figure 4 shows the 176-pin lqfp pinout for the spc563m64 (1536 kb flash memory). figure 4. 176-pin lqfp pinout (spc563m64; top view) 176 - pin lqfp nic an[37] an[36] an[21] an[0] (dan0+) an[1] (dan0?) an[2] (dan1+) an[3] (dan1?) an[4] (dan2+) an[5] (dan2?) an[6] (dan3+) an[7] (dan3?) refbypc vrh vrl an[22] an[23] an[24] an[25] an[27] an[28] an[30] an[31] an[32] an[33] an[34] an[35] vdd an[12] / ma[0] / etpu_a[19] / sds an[13] / ma[1] / etpu_a[21] / sdo an[14] / ma[2] / etpu_a[27] / sdi an[15] / fck / etpu_a[29] gpio[207] gpio[206] gpio[99] gpio[98] vss etpu_a[25] / gpio[223] vddeh7 etpu_a[21] / gpio[222] etpu_a[19] / gpio[221] etpu_a[13] / gpio[220] etpu_a[27] / gpio[224] vss nic etpu_a[13] / dspi_b_pcs[3] / gpio[127] etpu_a[12] / dspi_b_pcs[1] / gpio[126] etpu_a[11] / etpu_a[23] / gpio[125] etpu_a[10] / etpu_a[22] / gpio[124] etpu_a[9] / etpu_a[21] / gpio[123] etpu_a[8] / etpu_a[20] / dspi_b_sout_lvds+ / gpio[122] etpu_a[7] / etpu_a[19] / dspi_b_sout_lvds? / etpu_a[6] / gpio[121] etpu_a[6] / etpu_a[18] / dspi_b_sck_lvds+ / gpio[120] etpu_a[5] / etpu_a[17] / dspi_b_sck_lvds? / gpio[119] vddeh1b etpu_a[4] / etpu_a[16] / gpio[118] vss etpu_a[3] / etpu_a[15] / gpio[117] etpu_a[2] / etpu_a[14] / gpio[116] etpu_a[1] / etpu_a[13] / gpio[115] etpu_a[0] / etpu_a[12] / etpu_a[19] / gpio[114] vdd emios[0] / etpu_a[0] / etpu_a[25] / gpio[179] emios[1] / etpu_a[1] / gpio[180] emios[2] / etpu_a[2] / gpio[181] nic emios[4] / etpu_a[4] / gpio[183] nic nic emios[8] / etpu_a[8] / sci_b_tx / gpio[187] emios[9] / etpu_a[9] / sci_b_rx / gpio[188] vss emios[10] / gpio[189] vddeh6a emios[11] / gpio[190] emios[12] / dspi_c_sout / etpu_a[27] / gpio[191] emios[13] / gpio[192] emios[14] / irq [0] / etpu_a[29] / gpio[193] emios[15] / irq [1] / gpio[194] emios[23] / gpio[202] can_a_tx / sci_a_tx / gpio[83] can_a_rx / sci_a_rx / gpio[84 pllref / irq [4]/etrig[2] / gpio[208] sci_b_rx / gpio[92] bootcfg1 / irq [3] / etrig[3] / gpio[212] wkpcfg / nmi / dspi_b_sout / gpio[213] sci_b_tx / gpio[91] nic nic tms tdi / emios[5] / gpio[232] etpu_a[4] / gpio[227] tck vss etpu_a[2] / gpio[231] vddeh7 etpu_a[29] / gpio[225] tdo / emios[6] / gpio[228] gpio[219] jcomp alt_evto vdde12 alt_mseo [0] alt_mseo [1] alt_evti vss dspi_b_pcs[3] / dspi_c_sin / gpio[108] dspi_b_sout / dspi_c_pcs[5] / gpio[104] dspi_b_sin / dspi_c_pcs[2] / gpio[103] dspi_b_pcs[0] / gpio[105] vddeh6b dspi_b_pcs[1] / gpio[106] vss dspi_b_pcs[2] / dspi_c_sout / gpio[107] dspi_b_sck / dspi_c_pcs[1] / gpio[102] dspi_b_pcs[4] / dspi_c_sck / gpio[109] dspi_b_pcs[5] / dspi_c_pcs[0] / gpio[110] vdd rstout can_c_tx / gpio[87] sci_a_tx / emios[13] / gpio[89] sci_a_rx / emios[15] / gpio[90] can_c_rx / gpio[88] reset vss vddeh6a vsspll xtal extal / extclk vddpll vss nic an[18] an[17] an[16] an[11] / anz an[9] / anx vdda vssa an[39] / an[10] / any an[38] / an[8] / anw vddreg vrcctl vstby vrc33 alt_mcko vss vdde12 alt_mdo[0] alt_mdo[1] alt_mdo[2] alt_mdo[3] (see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28) vss (see signal details, pin 30) vddeh1a (see signal details, pin 32) vdd etpu_a[21] / irq [9] / gpio[135] etpu_a[20] / irq [8] / gpio[134] etpu_a[19] / gpio[133] etpu_a[18] / gpio[132] etpu_a[17] / gpio[131] etpu_a[16] / gpio[130] (see signal details, pin 40) vddeh1b (see signal details, pin 42) vss nic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 note: pins marked ?nic? have no internal connection. signal details: pin 21: etpu_a[31] / dspi_c_pcs[4] / etpu_a[13] / gpio[145] pin 22: etpu_a[30] / dspi_c_pcs[3] / etpu_a[11] / gpio[144] pin 23: etpu_a[29] / dspi_c_pcs[2] / gpio[143] pin 24: etpu_a[28] / dspi_c_pcs[1] / gpio[142] pin 25: etpu_a[27] / irq [15] / dspi_c_sout_lvds+ / dspi_b_sout / gpio[141] pin 26: etpu_a[26] / irq [14] / dspi_c_sout_lvds? / gpio[140] pin 27: etpu_a[25] / irq [13] / dspi_c_sck_lvds+ / gpio[139] pin 28: etpu_a[24] / irq [12] / dspi_c_sck_lvds? / gpio[138] pin 30: etpu_a[23] / irq [11] / etpu_a[21] / gpio[137] pin 32: etpu_a[22] / irq [10] / etpu_a[17] / gpio[136] pin 40: etpu_a[15] / dspi_b_pcs[5] / gpio[129] pin 42: etpu_a[14] / dspi_b_pcs[4] / etpu_a[9] / gpio[128]
spc563m64l5, spc563m64l7, spc563m60l5p, spc 563m60l7p pinout and signal description doc id 14642 rev 11 47/142 3.4 lqfp176 pinout (spc563m60) figure 5 shows the pinout for the 176-pin lqfp for the spc563m60 (1024 kb flash memory). figure 5. 176-pin lqfp pinout (spc563m60; top view) 176-pin lqfp nic nc nc an[21] an[0] (dan0+) an[1] (dan0-) an[2] (dan1+) an[3] (dan1-) an[4] (dan2+) an[5] (dan2-) an[6] (dan3+) an[7] (dan3-) refbypc vrh vrl an[22] an[23] an[24] an[25] an[27] an[28] an[30] an[31] an[32] an[33] an[34] an[35] vdd an[12] / ma[0] / etpu_a[19] / sds an[13] / ma[1] / etpu_a[21] / sdo an[14] / ma[2] / etpu_a[27] / sdi an[15] / fck / etpu_a[29] nc nc nc nc vss etpu_a[25] / gpio[223] vddeh7 etpu_a[21] / gpio[222] etpu_a[19] / gpio[221] etpu_a[13] / gpio[220] etpu_a[27] / gpio[224] vss nic etpu_a[13] / dspi_b_pcs[3] / gpio[127] etpu_a[12] / dspi_b_pcs[1] / gpio[126] etpu_a[11] / etpu_a[23] / gpio[125] etpu_a[10] / etpu_a[22] / gpio[124] etpu_a[9] / etpu_a[21] / gpio[123] etpu_a[8]/etpu_a[20]/dspi_b_sout_lvds+/gpio[122] etpu_a[7]/etpu_a[19]/dspi_b_sout_lvds-/etpu_a[6]/gpio[121] etpu_a[6] / etpu_a[18] / dspi_b_sck_lvds+ / gpio[120] etpu_a[5] / etpu_a[17] / dspi_b_sck_lvds- / gpio[119] vddeh1b etpu_a[4] / etpu_a[16] / gpio[118] vss etpu_a[3] / etpu_a[15] / gpio[117] etpu_a[2] / etpu_a[14] / gpio[116] etpu_a[1] / etpu_a[13] / gpio[115] etpu_a[0] / etpu_a[12] / etpu_a[19] / gpio[114] vdd emios[0] / etpu_a[0] / etpu_a[25] / gpio[179] nc emios[2] / etpu_a[2] / gpio[181] nic emios[4] / etpu_a[4] / gpio[183] nic nic emios[8] / etpu_a[8] / sci_b_tx / gpio[187] emios[9] / etpu_a[9] / sci_b_rx / gpio[188] vss emios[10] / gpio[189] vddeh6a emios[11] / gpio[190] emios[12] / dspi_c_sout / etpu_a[27] / gpio[191] nc emios[14] / irq [0] / etpu_a[29] / gpio[193] nc emios[23] / gpio[202] can_a_tx / sci_a_tx / gpio[83] can_a_rx / sci_a_rx / gpio[84] pllref / irq [4]/etrig[2] / gpio[208] sci_b_rx / gpio[92] bootcfg1 / irq [3] / etrig[3] / gpio[212] wkpcfg / nmi / dspi_b_sout / gpio[213] sci_b_tx / gpio[91] nic nic tms tdi / emios[5] / gpio[232] etpu_a[4] / gpio[227] tck vss etpu_a[2] / gpio[231] vddeh7 etpu_a[29] / gpio[225] tdo / emios[6] / gpio[228] gpio[219] jcomp alt_evto vdde12 alt_mseo [0] alt_mseo [1] alt_evti vss dspi_b_pcs[3] / dspi_c_sin / gpio[108] dspi_b_sout / dspi_c_pcs[5] / gpio[104] dspi_b_sin / dspi_c_pcs[2] / gpio[103] dspi_b_pcs[0] / gpio[105] vddeh6b dspi_b_pcs[1] / gpio[106] vss dspi_b_pcs[2] / dspi_c_sout / gpio[107] dspi_b_sck / dspi_c_pcs[1] / gpio[102] dspi_b_pcs[4] / dspi_c_sck / gpio[109] dspi_b_pcs[5] / dspi_c_pcs[0] / gpio[110] vdd rstout can_c_tx / gpio[87] sci_a_tx / emios[13] / gpio[89] sci_a_rx / emios[15] / gpio[90] can_c_rx / gpio[88] reset vss vddeh6a vsspll xtal extal / extclk vddpll vss nic an[18] an[17] an[16] an[11] / anz an[9] / anx vdda vssa an[39] / an[10] / any an[38] / an[8] / anw vddreg vrcctl vstby vrc33 alt_mcko vss vdde12 alt_mdo[0] alt_mdo[1] alt_mdo[2] alt_mdo[3] (see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28) vss (see signal details, pin 30) vddeh1a (see signal details, pin 32) vdd etpu_a[21] / irq [9] / gpio[135] etpu_a[20] / irq [8] / gpio[134] etpu_a[19] / gpio[133] etpu_a[18] / gpio[132] etpu_a[17] / gpio[131] etpu_a[16] / gpio[130] (see signal details, pin 40) vddeh1b (see signal details, pin 42) vss nic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 n otes: 1 . pins marked ?nic? have no internal connection. 2. pins marked ?nc? are not functional pins but may be connected to internal circuitry. connections to external circuits or oth er pins on this device can result in unpredictable system behavior or damage. signal details: pin 21: etpu_a[31] / dspi_c_pcs[4] / etpu_a[13] / gpio[145] pin 22: etpu_a[30] / dspi_c_pcs[3] / etpu_a[11] / gpio[144] pin 23: etpu_a[29] / dspi_c_pcs[2] / gpio[143] pin 24: etpu_a[28]/ dspi_c_pcs[1] / gpio[142] pin 25: etpu_a[27] / irq [15] / dspi_c_sout_lvds+ / dspi_b_sout / gpio[141] pin 26: etpu_a[26] / irq [14] / dspi_c_sout_lvds- / gpio[140] pin 27: etpu_a[25] / irq [13] / dspi_c_sck_lvds+ / gpio[139] pin 28: etpu_a[24] / irq [12] / dspi_c_sck_lvds- / gpio[138] pin 30: etpu_a[23] / irq [11] / etpu_a[21] / gpio[137] pin 32: etpu_a[22] / irq [10] / etpu_a[17] / gpio[136] pin 40: etpu_a[15] / dspi_b_pcs[5] / gpio[129] pin 42: etpu_a[14] / dspi_b_pcs[4] / etpu_a[9] / gpio[128]
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 48/142 doc id 14642 rev 11 3.5 lbga208 ballm ap (spc563m64) figure 6 shows the 208-pin lbga ballmap for the spc563m64 (1536 kb flash memory) as viewed from above. figure 6. 208-pin lbga ballmap (spc563m64; top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a vss an9 an11 vdda1 vssa1 an1 an5 vrh vrl an27 vssa0 an12- sds alt_ mdo2 alt_ mdo0 vrc33 vss b vdd vss an38 an21 an0 an4 refbypc an22 an25 an28 vdda0 an13-sdo alt_ mdo3 alt_ mdo1 vss vdd c vstby vdd vss an17 an34 an16 an3 an7 an23 an32 an33 an14-sdi an15 fck vss alt_ mseo 0 tck d vrc33 an39 vdd vss an18 an2 an6 an24 an 30 an31 an35 vddeh7 vss tms alt_evto nic (1) e etpua30 etpua31 an37 vdd vdde7 tdi alt_evti alt_ mseo 1 f etpua28 etpua29 etpua26 an36 vddeh6 tdo alt_mcko jcomp g etpua24 etpua27 etpua25 etpua21 vss vss vss vss dspi_b_ sout dspi_b_ pcs3 dspi_b_ sin dspi_b_ pcs0 h etpua23 etpua22 etpua17 etpua18 vss vss vss vss gpio99 dspi_b_ pcs4 dspi_b_ pcs2 dspi_b_ pcs1 j etpua20 etpua19 etpua14 etpua13 vss vss vss vss dspi_b_ pcs5 sci_a_tx gpio98 dspi_b_ sck k etpua16 etpua15 etpua7 vddeh1 vss vss vss vss can_c_ tx sci_a_rx rstout vddreg l etpua12 etpua11 etpua6 etpua0 sci_b_tx can_c_ rx wkpcfg reset m etpua10 etpua9 etpua1 etpua5 sci_b_rx pllref bootcfg1 vsspll n etpua8 etpua4 etpua0 vss vdd vrc33 emios2 emios10 vddeh1/6 (2) emios12 etpu_a19 (3) vrc33 vss vrcctl nic (1) extal p etpua3 etpua2 vss vdd gpio207 vdde7 nic (1) emios8 etpu_a29 ( 3) etpu_a2 (3) etpu_a21 ( 3) can_a_ tx vdd vss nic (1) xtal rnic (1) vss vdd gpio206 emios4 nic (1) emios9 emios11 emios14 etpu_a27 ( 3) emios23 can_a_ rx nic (1) vdd vss vddpll tvss vdd nic (1) emios0 emios1 gpio219 etpu_a25 ( 3) emios13 emios15 etpu_a4 (3) etpu_a13 ( 3) nic (1) vdde5 clkout vdd vss 1. pins marked ?nic? have no internal connection. 2. this ball may be changed to ?nc? (no connection) in a future revision. 3. etpu output only channel.
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 49/142 3.6 signal summary table 4. spc563mx signal properties name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208 dedicated gpio gpio[98] gpio pcr[98] ? i/o vddeh7 slow ? / up gpio[98]/up ? ? 141 (7) j15 gpio[99] gpio pcr[99] ? i/o vddeh7 slow ? / up gpio[99]/up ? ? 142 (7) h13 gpio[206] (8) gpio pcr[206] ? i/o vddeh7 slow ? / up gpio[206]/up ? ? 143 (7) r4 gpio[207] (8) gpio pcr[207] ? i/o vddeh7 slow ? / up gpio[207]/up ? ? 144 (7) p5 reset / configuration reset external reset input ? ? i vddeh6a slow i / up reset / up 58 80 97 l16 rstout external reset output pcr[230] ? o vddeh6a slow rstout/ low rstout/ high 61 85 102 k15 pllref irq [4] etrig[2] gpio[208] fmpll mode selection external interrupt request eqadc trigger input gpio pcr[208] 011 010 100 000 i i i i/o vddeh6a slow pllref / up ? / up 48 68 83 m14 bootcfg1 irq [3] etrig[3] gpio[212] boot config. input external interrupt request eqadc trigger input gpio pcr[212] 011 010 100 000 i i i i/o vddeh6a slow bootcfg1 / down ? / down 49 70 85 m15 wkpcfg nmi dspi_b_sout gpio[213] weak pull config. input non-maskable interrupt dspi_b data output gpio pcr[213] 01 11 10 00 i i o i/o vddeh6a slow wkpcfg / up ? / up 50 71 86 l15
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 50/142 doc id 14642 rev 11 calibration (9) cal_addr[12:15] (10) calibration address bus pcr[340] ? o vdde12 fast o / low cal_addr / low ??? ? cal_addr[16] (20) alt_mdo[0] (11) calibration address bus nexus msg data out pcr[345] ? o o vdde12 (12) vdde7 (13) fast o / low (14) mdo / alt_addr (11) / low ??17 a14 cal_addr[17] (20) alt_mdo[1] (11) calibration address bus nexus msg data out pcr[345] ? o o vdde12 (12) vdde7 (13) fast o / low (14) alt_mdo / cal_addr (11) / low ??18 b14 cal_addr[18] (20) alt_mdo[2] (11) calibration address bus nexus msg data out pcr[345] ? o o vdde12 (12) vdde7 (13) fast o / low (14) alt_mdo / cal_addr (11) / low ??19 a13 cal_addr[19] (20) alt_mdo[3] (11) calibration address bus nexus msg data out pcr[345] ? o o vdde12 (12) vdde7 (13) fast o / low (14) alt_mdo / cal_addr (11) / low ??20 b13 cal_addr[20:27] alt_mdo[4:11] calibration address bus nexus msg data out pcr[345] ? o o vdde12 (12) fast o / low alt_mdo / cal_addr (15) / low ??? ? cal_addr[28] (20) alt_mseo [0] (11) calibration address bus nexus msg start/end out pcr[345] ? o o vdde12 (12) vdde7 (13) fast o / low (16) alt_mseo (15) / cal_addr (16) / low ? ? 118 c15 cal_addr[29] (20) alt_mseo [1] (11) calibration address bus nexus msg start/end out pcr[345] ? o o vdde12 (12) vdde7 (13) fast o / low (16) alt_mseo (15) / cal_addr (16) / low ? ? 117 e16 cal_addr[30] (20) alt_evti (11) calibration address bus nexus event in pcr[345] ? o i vdde12 (12) vdde7 (13) fast ? (17) alt_evti / cal_addr (18) ? ? 116 e15 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 51/142 alt_evto nexus event out pcr[344] ? o vdde12 (12) vdde7 (13) fast o / low alt_evto / high ? ? 120 d15 alt_mcko nexus msg clock out pcr[344] ? o vdde12 (12) vdde7 (13) fast o / low alt_mcko / enabled ??14 f15 nexuscfg (10) nexus/calibration bus selector ??i vdde12 fast i / down nexuscfg / down ??? ? cal_cs [0] (10) calibration chip selects pcr[336] ? o vdde12 fast o / high cal_cs / high ? ? ? ? cal_cs [2] (10) cal_addr[10] calibration chip selects calibration address bus pcr[338] 11 10 o o vdde12 fast o / high cal_cs / high ? ? ? ? cal_cs [3] (10) cal_addr[11] calibration chip selects calibration address bus pcr[339] 11 10 o o vdde12 fast o / high cal_cs / high ? ? ? ? cal_data[0:9] (10) calibration data bus pcr[341] i/o vdde12 fast ? / up ? / up ? ? ? ? cal_data[10:15] (10) calibration data bus pcr[341] i/o vdde12 fast ? / up ? / up ? ? ? ? cal_oe (10) calibration output enable pcr[342] ? o vdde12 fast o / high cal_oe / high ? ? ? ? cal_rd_wr (10) calibration read/write pcr[342] ? o vdde12 fast o / high cal_rd_wr /high ??? ? cal_ts _ale (10) calibration transfer start address latch enable pcr[343] ts=0b1 ale=0b 0 o o vdde12 fast o / high cal_ts / high ? ? ? ? cal_we _be[0:1] (10) calibration write enable byte enable pcr[342] ? o vdde12 fast o / high cal_we / high ??? ? nexus (19) table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 52/142 doc id 14642 rev 11 evti (20) etpu_a[2] gpio[231] nexus event in etpu a ch. gpio pcr[231] 01 10 00 i o i/o vddeh7 multi-v ? / ? ? / ? ? 103 126 p10 evto (20) etpu_a[4] gpio[227] nexus event out etpu a ch. gpio pcr[227] 01 (21) 10 00 o o i/o vddeh7 multi-v i / up i / up ? 106 129 t10 mcko (20) gpio[219] nexus msg clock out gpio pcr[219] n/a (21) 00 o i/o vddeh7 multi-v ? / ? ? / ? ? 99 122 t6 mdo[0] (20) etpu_a[13] gpio[220] nexus msg data out etpu a ch. gpio pcr[220] 01 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? ? 110 135 t11 mdo[1] (20) etpu_a[19] gpio[221] nexus msg data out etpu a ch. gpio pcr[221] 01 (21) 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? ? 111 136 n11 mdo[2] (20) etpu_a[21] gpio[222] nexus msg data out etpu a ch. gpio pcr[222] 01 (21) 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? ? 112 137 p11 mdo[3] (20) etpu_a[25] gpio[223] nexus msg data out etpu a ch. gpio pcr[223] 01 (21) 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? ? 114 139 t7 mseo [0] (20) etpu_a[27] gpio[224] nexus msg start/end out etpu a ch. gpio pcr[224] 01 (21) 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? ? 109 134 r10 mseo [1] (20) etpu_a[29] gpio[225] nexus msg start/end out etpu a ch. gpio pcr[225] 01 (21) 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? ? 101 124 p9 jtag / test t c k j tag te s t c l o ck i n p u t ? ? i vddeh7 multi-v tck / down tck / down 73 105 128 c16 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 53/142 tdi (22) emios[5] gpio[232] jtag test data input emios ch. gpio pcr[232] 01 (23) 10 00 i o i/o vddeh7 multi-v ? / ? ? / ? 74 107 130 e14 tdo (22) emios[6] gpio[228] jtag test data output emios ch. gpio pcr[228] 01 (23) 10 00 o o i/o vddeh7 multi-v ? / ? ? / ? 70 100 123 f14 tms jtag test mode select input ? ? i vddeh7 multi-v tms / up tms / up 75 108 131 d14 jcomp jtag tap controller enable ? ? i vddeh7 multi-v jcomp / down jcomp / down 69 98 121 f16 can can_a_tx sci_a_tx gpio[83] can_a transmit esci_a transmit gpio pcr[83] 01 10 00 o o i/o vddeh6a slow ? / up ? / up (24) 46 66 81 p12 can_a_rx sci_a_rx gpio[84] can_a receive esci_a receive gpio pcr[84] 01 10 00 i i i/o vddeh6a slow ? / up ? / up 47 67 82 r12 can_c_tx gpio[87] can_c transmit gpio pcr[87] 01 00 o i/o vddeh6a medium ? / up ? / up 60 84 101 k13 can_c_rx gpio[88] can_c receive gpio pcr[88] 01 00 i i/o vddeh6a slow ? / up ? / up 59 81 98 l14 esci sci_a_tx emios[13] gpio[89] esci_a transmit emios ch. gpio pcr[89] 01 10 00 o o i/o vddeh6a slow ? / up ? / up ? 83 100 j14 sci_a_rx (25) emios[15] gpio[90] esci_a receive emios ch. gpio pcr[90] 01 10 00 i o i/o vddeh6a slow ? / up ? / up ? 82 99 k14 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 54/142 doc id 14642 rev 11 sci_b_tx gpio[91] esci_b transmit gpio pcr[91] 01 00 i/o i/o vddeh6a slow ? / up ? / up ? 72 87 l13 sci_b_rx gpio[92] esci_b receive gpio pcr[92] 01 00 i i/o vddeh6a slow ? / up ? / up ? 69 84 m13 dspi dspi_b_sck dspi_c_pcs[1] gpio[102] dspi_b clock dspi_c periph chip select gpio pcr[102] 01 10 00 i/o o i/o vddeh6b medium ? / up ? / up 64 89 106 j16 dspi_b_sin dspi_c_pcs[2] gpio[103] dspi_b data input dspi_c periph chip select gpio pcr[103] 01 10 00 i o i/o vddeh6b medium ? / up ? / up 67 95 112 g15 dspi_b_sout dspi_c_pcs[5] gpio[104] dspi_b data output dspi_c periph chip select gpio pcr[104] 01 10 00 o o i/o vddeh6b medium ? / up ? / up ? 96 113 g13 dspi_b_pcs[0] gpio[105] dspi_b periph chip select gpio pcr[105] 01 00 o i/o vddeh6b medium ? / up ? / up ? 94 111 g16 dspi_b_pcs[1] gpio[106] dspi_b periph chip select gpio pcr[106] 01 00 o i/o vddeh6b medium ? / up ? / up ? 92 109 h16 dspi_b_pcs[2] dspi_c_sout gpio[107] dspi_b periph chip select dspi_c data output gpio pcr[107] 01 10 00 o o i/o vddeh6b medium ? / up ? / up ? 90 107 h15 dspi_b_pcs[3] dspi_c_sin gpio[108] dspi_b periph chip select dspi_c data input gpio pcr[108] 01 10 00 o i i/o vddeh6b medium ? / up ? / up 68 97 114 g14 dspi_b_pcs[4] dspi_c_sck gpio[109] dspi_b periph chip select dspi_c clock gpio pcr[109] 01 10 00 o i/o i/o vddeh6b medium ? / up ? / up 63 88 105 h14 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 55/142 dspi_b_pcs[5] dspi_c_pcs[0] gpio[110] dspi_b periph chip select dspi_c periph chip select gpio pcr[110] 01 10 00 o o i/o vddeh6b medium ? / up ? / up ? 87 104 j13 eqadc an[0] (26) dan0+ single ended analog input positive terminal diff. input ?? i i vdda i / ? an[0] / ? 99 143 172 b5 an[1] (26) dan0- single ended analog input negative terminal diff. input ?? i i vdda i / ? an[1] / ? 98 142 171 a6 an[2] (26) dan1+ single ended analog input positive terminal diff. input ?? i i vdda i / ? an[2] / ? 97 141 170 d6 an[3] (26) dan1- single ended analog input negative terminal diff. input ?? i i vdda i / ? an[3] / ? 96 140 169 c7 an[4] (26) dan2+ single ended analog input positive terminal diff. input ?? i i vdda i / ? an[4] / ? 95 139 168 b6 an[5] (26) dan2- single ended analog input negative terminal diff. input ?? i i vdda i / ? an[5] / ? 94 138 167 a7 an[6] (26) dan3+ single ended analog input positive terminal diff. input ?? i i vdda i / ? an[6] / ? 93 137 166 d7 an[7] (26) dan3- single ended analog input negative terminal diff. input ?? i i vdda i / ? an[7] / ? 92 136 165 c8 an[8] see an[38]-an[8]-anw an[9] anx single ended analog input external multiplexed analog input ?? i i vdda i / ? an[9] / ? 2 5 5 a2 an[10] see an[39]-an[10]-any an[11] anz single ended analog input external multiplexed analog input ?? i i vdda i / ? an[11] / ? 1 4 4 a3 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 56/142 doc id 14642 rev 11 an[12] ma[0] etpu_a[19] sds single ended analog input mux address etpu_a ch. eqadc serial data strobe pcr[215] 011 010 100 000 i o o o vddeh7 i / ? an[12] / ? 81 119 148 a12 an[13] ma[1] etpu_a[21] sdo single ended analog input mux address etpu_a ch. eqadc serial data out pcr[216] 011 010 100 000 i o o o vddeh7 i / ? an[13] / ? 80 118 147 b12 an[14] ma[2] etpu_a[27] sdi single ended analog input mux address etpu_a ch. eqadc serial data in pcr[217] 011 010 100 000 i o o i vddeh7 i / ? an[14] / ? 79 117 146 c12 an[15] fck etpu_a[29] single ended analog input eqadc free running clock etpu_a ch. pcr[218] 011 010 000 i o o vddeh7 i / ? an[15] / ? 78 116 145 c13 an[16] single ended analog input ? ? i vdda i / ? an[x] / ? ? 3 3 c6 an[17] single ended analog input ? ? i vdda i / ? an[x] / ? ? 2 2 c4 an[18] single ended analog input ? ? i vdda i / ? an[x] / ? ? 1 1 d5 an[21] single ended analog input ? ? i vdda i / ? an[x] / ? 100 144 173 b4 an[22] single ended analog input ? ? i vdda i / ? an[x] / ? ? 132 161 b8 an[23] single ended analog input ? ? i vdda i / ? an[x] / ? 88 131 160 c9 an[24] single ended analog input ? ? i vdda i / ? an[x] / ? ? 130 159 d8 an[25] single ended analog input ? ? i vdda i / ? an[x] / ? 87 129 158 b9 an[27] single ended analog input ? ? i vdda i / ? an[x] / ? ? 128 157 a10 an[28] single ended analog input ? ? i vdda i / ? an[x] / ? 86 127 156 b10 an[30] single ended analog input ? ? i vdda i / ? an[x] / ? ? 126 155 d9 an[31] single ended analog input ? ? i vdda i / ? an[x] / ? 85 125 154 d10 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 57/142 an[32] single ended analog input ? ? i vdda i / ? an[x] / ? ? 124 153 c10 an[33] single ended analog input ? ? i vdda i / ? an[x] / ? 84 123 152 c11 an[34] single ended analog input ? ? i vdda i / ? an[x] / ? ? 122 151 c5 an[35] single ended analog input ? ? i vdda i / ? an[x] / ? 83 121 150 d11 an[36] single ended analog input ? ? i vdda i / ? an[x] / ? ? ? 174 (7) f4 (8) an[37] single ended analog input ? ? i vdda i / ? an[x] / ? ? ? 175 (7) e3 (8) an[38]-an[8]- anw single ended analog input multiplexed analog input ? ? i vdda i / ? an[38] / ? 6 9 9 b3 an[39]-an[10]- any single ended analog input multiplexed analog input ? ? i vdda i / ? an[39] / ? 5 8 8 d2 vrh voltage reference high ? ? i vdda ? / ? vrh 90 134 163 a8 vrl voltage reference low ? ? i vssa0 ? / ? vrl 89 133 162 a9 refbypc bypass capacitor input ? ? i vrl ? / ? refbypc 91 135 164 b7 etpu2 etpu_a[0] etpu_a[12] etpu_a[19] gpio[114] etpu_a ch. etpu_a ch. etpu_a ch. gpio pcr[114] 011 010 100 000 i/o o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 37 52 61 l4, n3 etpu_a[1] etpu_a[13] gpio[115] etpu_a ch. etpu_a ch. gpio pcr[115] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 36 51 60 m3 etpu_a[2] etpu_a[14] gpio[116] etpu_a ch. etpu_a ch. gpio pcr[116] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 35 50 59 p2 etpu_a[3] etpu_a[15] gpio[117] etpu_a ch. etpu_a ch. gpio pcr[117] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 34 49 58 p1 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 58/142 doc id 14642 rev 11 etpu_a[4] etpu_a[16] gpio[118] etpu_a ch. etpu_a ch. gpio pcr[118] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 32 47 56 n2 etpu_a[5] etpu_a[17] dspi_b_sck_lvds- gpio[119] etpu_a ch. etpu_a ch. dspi_b clock lvds- gpio pcr[119] 001 010 100 000 i/o o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 30 45 54 m4 etpu_a[6] etpu_a[18] dspi_b_sck_lvds+ gpio[120] etpu_a ch. etpu_a ch. dspi_b clock lvds+ gpio pcr[120] 001 010 100 000 i/o o o i/o vddeh1b medium ? / wkpcfg ? / wkpcfg 29 44 53 l3 etpu_a[7] etpu_a[19] dspi_b_sout_lvds- etpu_a[6] gpio[121] etpu_a ch. etpu_a ch. dspi_b data output lvds- etpu_a ch. gpio pcr[121] 0001 0010 0100 1000 0000 i/o o o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 28 43 52 k3 etpu_a[8] etpu_a[20] dspi_b_sout_lvds+ gpio[122] etpu_a ch. etpu_a ch. dspi_b data output lvds+ gpio pcr[122] 001 010 100 000 i/o o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 27 42 51 n1 etpu_a[9] etpu_a[21] gpio[123] etpu_a ch. etpu_a ch. gpio pcr[123] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 41 50 m2 etpu_a[10] etpu_a[22] gpio[124] etpu_a ch. etpu_a ch. gpio pcr[124] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 40 49 m1 etpu_a[11] etpu_a[23] gpio[125] etpu_a ch. etpu_a ch. gpio pcr[125] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 39 48 l2 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 59/142 etpu_a[12] dspi_b_pcs[1] gpio[126] etpu_a ch. dspi_b periph chip select gpio pcr[126] 01 10 00 i/o o i/o vddeh1b medium ? / wkpcfg ? / wkpcfg ? 38 47 l1 etpu_a[13] dspi_b_pcs[3] gpio[127] etpu_a ch. dspi_b periph chip select gpio pcr[127] 01 10 00 i/o o i/o vddeh1b medium ? / wkpcfg ? / wkpcfg 26 37 46 j4 etpu_a[14] dspi_b_pcs[4] etpu_a[9] gpio[128] etpu_a ch. dspi_b periph chip select etpu_a ch. gpio pcr[128] 001 010 100 000 i/o o o i/o vddeh1b medium ? / wkpcfg ? / wkpcfg 24 35 42 j3 etpu_a[15] dspi_b_pcs[5] gpio[129] etpu_a ch. dspi_b periph chip select gpio pcr[129] 01 10 00 i/o o i/o vddeh1b medium ? / wkpcfg ? / wkpcfg 22 33 40 k2 etpu_a[16] gpio[130] etpu_a ch. gpio pcr[130] 01 00 i/o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 32 39 k1 etpu_a[17] gpio[131] etpu_a ch. gpio pcr[131] 01 00 i/o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 31 38 h3 etpu_a[18] gpio[132] etpu_a ch. gpio pcr[132] 01 00 i/o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 30 37 h4 etpu_a[19] gpio[133] etpu_a ch. gpio pcr[133] 01 00 i/o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 29 36 j2 etpu_a[20] irq [8] gpio[134] etpu_a ch. external interrupt request gpio pcr[134] 01 10 00 i/o i i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 28 35 j1 etpu_a[21] irq [9] gpio[135] etpu_a ch. external interrupt request gpio pcr[135] 01 10 00 i/o i i/o vddeh1a slow ? / wkpcfg ? / wkpcfg ? 27 34 g4 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 60/142 doc id 14642 rev 11 etpu_a[22] irq [10] etpu_a[17] gpio[136] etpu_a ch. external interrupt request etpu_a ch. external gpio pcr[136] 001 010 100 000 i/o i o i/o vddeh1a slow ? / wkpcfg ? / wkpcfg ? 25 32 h2 etpu_a[23] irq [11] etpu_a[21] gpio[137] etpu_a ch. external interrupt request etpu_a ch. external gpio pcr[137] 001 010 100 000 i/o i o i/o vddeh1a slow ? / wkpcfg ? / wkpcfg ? 23 30 h1 etpu_a[24] (27) irq [12] dspi_c_sck_lvds- gpio[138] etpu_a ch. external interrupt request dspi_c clock lvds- gpio pcr[138] 001 010 100 000 i/o i o i/o vddeh1a slow ? / wkpcfg ? / wkpcfg 18 21 28 g1 etpu_a[25] (27) irq [13] dspi_c_sck_lvds+ gpio[139] etpu_a ch. external interrupt request dspi _c clock lvds+ gpio pcr[139] 001 010 100 000 i/o i o i/o vddeh1a medium ? / wkpcfg ? / wkpcfg 17 20 27 g3 etpu_a[26] (27) irq [14] dspi_c_sout_lvds- gpio[140] etpu_a ch. external interrupt request dspi_c data output lvds- gpio pcr[140] 001 010 100 000 i/o i o i/o vddeh1a slow ? / wkpcfg ? / wkpcfg 16 19 26 f3 etpu_a[27] (27) irq [15] dspi_c_sout_lvds+ dspi_b_sout gpio[141] etpu_a ch. external interrupt request dspi_c data output lvds+ dspi_b data output gpio pcr[141] 0001 0010 0100 1000 0000 i/o i o o i/o vddeh1a slow ? / wkpcfg ? / wkpcfg 15 18 25 g2 etpu_a[28] (27) dspi_c_pcs[1] gpio[142] etpu_a ch. (input and output) dspi_c periph chip select gpio pcr[142] 10 01 00 i/o o i/o vddeh1a medium ? / wkpcfg ? / wkpcfg 14 17 24 f1 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 61/142 etpu_a[29] (27) dspi_c_pcs[2] gpio[143] etpu_a ch. (input and output) dspi_c periph chip select gpio pcr[143] 10 01 00 i/o o i/o vddeh1a medium ? / wkpcfg ? / wkpcfg 13 16 23 f2 etpu_a[30] dspi_c_pcs[3] etpu_a[11] gpio[144] etpu_a ch. dspi_c periph chip select etpu_a ch. gpio pcr[144] 011 010 001 000 i/o o o i/o vddeh1a medium ? / wkpcfg ? / wkpcfg 12 15 22 e1 etpu_a[31] dspi_c_pcs[4] etpu_a[13] gpio[145] etpu_a ch. dspi_c periph chip select etpu_a ch. gpio pcr[145] 011 010 001 000 i/o o o i/o vddeh1a medium ? / wkpcfg ? / wkpcfg 11 14 21 e2 emios emios[0] etpu_a[0] etpu_a[25] (28) gpio[179] emios ch. etpu_a ch. etpu_a ch. gpio pcr[179] 001 010 100 000 i/o o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg 39 54 63 t4 emios[1] etpu_a[1] gpio[180] emios ch. etpu_a ch. gpio pcr[180] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? ? 64 (7) t5 (8) emios[2] etpu_a[2] gpio[181] emios ch. etpu_a ch. gpio pcr[181] 01 10 00 i/o o i/o vddeh1b slow ? / wkpcfg ? / wkpcfg ? 55 65 n7 emios[4] etpu_a[4] gpio[183] emios ch. etpu_a ch. gpio pcr[183] 01 10 00 i/o o i/o vddeh6a slow ? / wkpcfg ? / wkpcfg ? 56 67 r5 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 62/142 doc id 14642 rev 11 emios[8] etpu_a[8] (29) sci_b_tx gpio[187] emios ch. etpu_a ch. esci_b transmit gpio pcr[187] 001 010 100 000 i/o o o i/o vddeh6a slow ? / wkpcfg ? / wkpcfg 40 57 70 p8 emios[9] etpu_a[9] (29) sci_b_rx gpio[188] emios ch. etpu_a ch. esci_b receive gpio pcr[188] 001 010 100 000 i/o o i i/o vddeh6a slow ? / wkpcfg ? / wkpcfg 41 58 71 r7 emios[10] gpio[189] emios ch. gpio pcr[189] 01 00 i/o i/o vddeh6a slow ? / wkpcfg ? / wkpcfg ? 60 73 n8 emios[11] gpio[190] emios ch. gpio pcr[190] 01 00 i/o i/o vddeh6a slow ? / wkpcfg ? / wkpcfg ? 62 75 r8 emios[12] dspi_c_sout etpu_a[27] gpio[191] emios ch. dspi c data output etpu_a ch. gpio pcr[191] 001 010 100 000 i/o o o i/o vddeh6a medium ? / wkpcfg ? / wkpcfg 44 63 76 n10 emios[13] gpio[192] emios ch. gpio pcr[192] 01 00 i/o i/o vddeh6a ? / wkpcfg ? / wkpcfg ? ? 77 (7) t8 (8) emios[14] irq [0] etpu_a[29] gpio[193] emios ch. external interrupt request etpu_a ch. gpio pcr[193] 001 010 100 000 o i o i/o vddeh6a slow ? / wkpcfg ? / wkpcfg 45 64 78 r9 emios[15] irq [1] gpio[194] emios ch. external interrupt request gpio pcr[194] 01 10 00 o i i/o vddeh6a slow ? / wkpcfg ? / wkpcfg ? ? 79 (7) t9 (8) emios[23] gpio[202] emios ch. gpio pcr[202] 01 00 i/o i/o vddeh6a slow ? / wkpcfg ? / wkpcfg ? 65 80 r11 clock synthesizer xtal crystal oscillator output ? ? o vddeh6a o / ? xtal (30) / ? 54 76 93 p16 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 63/142 extal extclk crystal oscillator input external clock input ? ? i vddeh6a i / ? extal (31) / ? 53 75 92 n16 clkout system clock output pcr[229] ? o vdde5 fast clkout / enabled clkout / enabled ??? t14 power / ground vddpll pll supply voltage ? ? i vddpll (1.2v) i / ? ? 52 74 91 r16 vsspll (32) pll ground ? ? i vsspll i / ? ? 55 77 94 m16 vstby power supply for standby ram ? ? i vstby i / ? ? 9 12 12 c1 vrc33 3.3v voltage regulator bypass capacitor ? ? o vrc33 o / ? ? 10 13 13 a15, d1, n6, n12 vrcctl voltage regulator control output ? ? o na o / ? ? 8 11 11 n14 vdda (33) analog power input for eqadc ? ? i vdda (5.0 v) i / ? ? 3 6 6 ? vdda0 analog power input for eqadc ? ? i vdda i / ? ? ? ? ? b11 vssa0 analog ground input for eqadc ? ? i vssa i / ? ? ? ? ? a11 vdda1 analog power input for eqadc ? ? i vdda i / ? ? ? ? ? a4 vssa1 analog ground input for eqadc ? ? i vssa i / ? ? ? ? ? a5 vssa (34) analog ground input for eqadc ? ? i vssa i / ? ? 4 7 7 ? vddreg voltage regulator supply ? ? i vddreg (5.0 v) i / ? ? 7 10 10 k16 table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 64/142 doc id 14642 rev 11 vdd internal logic supply input ? ? i vdd (1.2 v) i / ? ? 21, 38, 62, 82 26, 53, 86, 120 33, 62, 103, 149 b1, b16, c2, d3, e4, n5, p4, p13, r3, r14, t2, t15 vss ground ? ? ? vss0 i / ? ? 19, 25, 33, 42, 51, 57, 65, 72, 77 22, 36, 48, 59, 73, 79, 91, 104, 115 15, 29, 43, 57, 72, 90, 96, 108, 115 7 , 127, 133, 140 a1, a16, b2, b15, c3, c14, d4, d13, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, n4, n13, p3, p14, r2, r15, t1, t16 vddeh1a (35) vddeh1b (35) i/o supply input ? ? i vddeh1 (36) (3.3v ? 5.0v) i / ? ? 20, 23 31 24, 34, 46 31, 41 55 k4 vdde5 i/o supply input ? ? i vdde5 i / ? ? ? ? ? t13 vddeh6a (37), (38) vddeh6b (38) i/o supply input ? ? i vddeh6 (3.3v ? 5.0v) i / ? ? 56, 66, 43 78, 93, 61 95, 110, 74 ? vddeh6 i/o supply input ? ? i vddeh6 i / ? ? ? ? ? f13 vddeh7 i/o supply input ? ? i vddeh7 (39) (3.3v ? 5.0v) i / ? ? 71, 76 102, 113 125, 138 d12 vdde7 (40) i/o supply input ? ? i vdde7 (3.3v) i / ? ? ? ? 16, 119 (7) e13, p6 1. for each pin in the table, each line in the function column is a separate function of the pin. for all i/o pins the selection of primary pin function or secondary function or gpio is done in the siu except where explicitly noted. table 4. spc563mx signal properties (continued) name function (1) pad config. register (pcr) (2) pcr pa field (3) i/o type voltage (4) / pad type reset state (5) function / state after reset (6) pin no. lqfp 100 lqfp 144 lqfp 176 lbga208
spc563m64l5, spc563m64l7, spc563m60l5p, sp c563m60l7p pinout and signal description doc id 14642 rev 11 65/142 2. values in this column refer to registers in the system integr ation unit (siu). the actual r egister name is ?siu_pcr? suffixed by the pcr number. for example, pcr[190] refers to the siu register named siu_pcr190. 3. the pad configuration register (pcr) pa fiel d is used by software to select pin function. 4. the vdde and vddeh supply inputs are broken into segments. each segment of slow i/o pins (vdd eh) may have a separate supply i n the 3.3 v to 5.0 v range (? 10%/+5%). each segment of fast i/o (vdde) may have a separate supply in the 1.8 v to 3.3 v range (+/? 10%). 5. terminology is o ? output, i ? input, up ? weak pull up enabled, down ? weak pull down enabled, low ? output driven low, high ? output driven high. a dash for the function in this column denotes that both the input and output buffer are turned off. 6. function after reset of gpi is general pur pose input. a dash for the function in this column denotes that both the input and output buffer are turned off. 7. not available on 1 mb version of 176-pin package. 8. the gpio functions on gpio[206] and gpio[ 207] can be selected as trigger functions in the siu for the adc by making the prope r selections in the siu_etisr and siu_isel3 registers in the siu. 9. some signals in this section are available only on calibration package. 10. these pins are only available in the 496 csp/mapbga calibration/development package. 11. on the calibration package, the nexus function on this pin is enabled when the nexuscfg pin is high and nexus is configured to full port mode. on the 176-pin and 208- pin packages, the nexus function on this pin is enabled permanently. do not connect the nexu s mdo or mseo pins directly to a po wer supply or ground. 12. in the calibration package, the i/o segm ent containing this pin is called vdde12. 13. 208-ball bga package only 14. when configured as nexus (208-pin package or calibration package with nexuscfg=1), and jcomp is asserted during reset, mdo[0 ] is driven high until the crystal oscillator becomes stable, at which time it is then negated. 15. the function of this pin is nexus when nexuscfg is high. 16. high when the pin is configured to nexus, low otherwise. 17. o/low for the calibration with nexuscfg=0; i/up otherwise. 18. alt_addr/low for the calibration package with nexuscfg=0; evti /up otherwise. 19. in 176-pin and 208-pin packages, the nexus function is disabled and the pin/ball has the secondary function 20. this signal is not available in the 176-pin and 208-pin packages. 21. the primary function is not selected via the pa field when the pi n is a nexus signal. instead, it is activated by the nexus controller. 22. tdi and tdo are requir ed for jtag operation. 23. the primary function is not selected via the pa field when the pi n is a jtag signal. instead, it is activated by the jtag co ntroller. 24. the function and state of the can_a and esci_a pins after ex ecution of the bam program is determined by the bootcfg1 pin. 25. connect an external 10k pull-up resistor to the sci_a_rx pin to ensure that the pin is driven high during can serial boot. 26. for pins an[0:7], during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pull resistors are disabled when the system clock propagates through the device. 27. etpua[24:29] are input and output. the input muxing is controlled by siu_isel8 register. 28. etpu_a[25] is an output only function. 29. only the output channels of etpu[8:9] are connected to pins. 30. the function after reset of the xtal pin is determined by the value of the signal on the pllcfg [1] pin. when bypass mode is chosen xtal has no function and should be grounded.
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 66/142 doc id 14642 rev 11 31. the function after reset of the extal_extclk pin is determined by the value of the signal on the pllcfg[1] pin. if the extcl k function is chosen, the valid operating voltage for the pin is 1.62 v to 3.6 v. if the extal func tion is chosen, the valid operating voltage is 3.3 v. 32. vsspll and vssreg are connected to the same pin. 33. this pin is shared by two pads: vdda_an, using pad_vdde_hv, and vdda _dig, using pad_vdde_int_hv. 34. this pin is shared by two pads: vssa_an, using pad_vsse_hv, and vssa_dig, using pad_vsse_int_hv. 35. vddeh1a, vddeh1b, and vddeh1ab are shorted together in all production packages. the separation of the signal names is presen t to support legacy naming, however they should be considered as th e same signal in this document. 36. lvds pins will not work at 3.3 v. 37. the vddeh6 segment may be powered from 3.0 v to 5.0 v for mux addr ess or ssi functions, but must meet the vdda specifications of 4.5 v to 5.25 v for analog input function. 38. vddeh6a and vddeh6b are shorted together in all production packages. th e separation of the signal names is present to suppor t legacy naming, however they should be considered as the same signal in this document. 39. if using jtag or nexus, the i/o segment t hat contains the jtag and nexus pins must be powered by a 5 v supply. the 3.3 v nexus /jtag signals are der ived from the 5 volt power supply. 40. in the calibration package this signal is named vdde12.
spc563m64l5, spc563m64l7, spc563m60l5p, spc 563m60l7p pinout and signal description doc id 14642 rev 11 67/142 3.7 signal details ta bl e 6 contains details on the multiplexed signals that appear in ta b l e 4 . table 5. pad types pad type name supply voltage slow pad_ssr_hv 3.0 v ? 5.25 v medium pad_msr_hv 3.0 v ? 5.25 v fast pad_fc 3.0 v ? 3.6 v multiv pad_multv_hv 3.0 v ? 5.25 v (high swing mode) 4.5 v ? 5.25 v (low swing mode) analog pad_ae_hv 0.0 ? 5.25 v lvds pad_lo_lv ? table 6. signal details signal module or function description clkout clock generation spc563mxx clock output for the external/calibration bus interface extal clock generation input pin for an external crystal oscillator or an external clock source based on the value driven on the pllref pin at reset. extclk clock generation external clock input pllref clock generation pllref is used to select whethe r the oscillator operates in xtal mode or external reference mode from reset. pllref=0 selects external reference mode. xtal clock generation crystal oscillator input sck_b_lvds? sck_b_lvds+ dspi lvds pair used for dspi_b tsb mode transmission sout_b_lvds? sout_b_lvds+ dspi lvds pair used for dspi_b tsb mode transmission sck_c_lvds? sck_c_lvds+ dspi lvds pair used for dspi_c tsb mode transmission sout_c_lvds? sout_c_lvds+ dspi lvds pair used for dspi_c tsb mode transmission pcs_b[0] pcs_c[0] dspi_b ? dspi_c peripheral chip select when device is in master mode?slave select when used in slave mode pcs_b[1:5] pcs_c[1:5] dspi_b ? dspi_c peripheral chip select when device is in master mode?not used in slave mode sck_b sck_c dspi_b ? dspi_c dspi clock?output when device is in master mode; input when in slave mode sin_b sin_c dspi_b ? dspi_c dspi data in
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 68/142 doc id 14642 rev 11 sout_b sout_c dspi_b ? dspi_c dspi data out cal_addr[12:30] calibration bus the cal_addr[12:30] signals spec ify the physical address of the bus transaction. cal_cs [0:3] calibration bus cs x is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the primary external bus. cal_data[0:15] calibration bus the cal_data[0:15] signals contain the data to be transferred for the current transaction. cal_oe calibration bus oe is used to indicate when an external memory is permitted to drive back read data. external memories must have their data output buffers off when oe is negated. oe is only asserted for chip-select accesses. cal_rd_wr calibration bus rd_wr indicates whether the current transaction is a read access or a write access. cal_ts _ale calibration bus the transfer start signal (ts ) is asserted by the spc563mxx to indicate the start of a transfer. the address latch enable (ale) signal is used to demultiplex the address from the data bus. cal_evto calibration bus nexus event out cal_mcko calibration bus nexus message clock out nexuscfg nexus/calibration bus nexus/calibration bus selector emios[0:23] emios emios i/o channels an[0:39] eqadc single-ended analog inputs for analog-to-digital converter fck eqadc eqadc free running clock for eqadc ssi. ma[0:2] eqadc these three control bits are output to enable the selection for an external analog mux for expansion channels. refbypc eqadc bypass capacitor input sdi eqadc serial data in sdo eqadc serial data out sds eqadc serial data select vrh eqadc voltage reference high input vrl eqadc voltage reference low input sci_a_rx sci_b_rx esci_a ? esci_b esci receive sci_a_tx sci_b_tx esci_a ? esci_b esci transmit etpu_a[0:31] etpu etpu i/o channel table 6. signal details (continued) signal module or function description
spc563m64l5, spc563m64l7, spc563m60l5p, spc 563m60l7p pinout and signal description doc id 14642 rev 11 69/142 can_a_tx can_c_tx flexcan_a ? flexcan_c flexcan transmit can_a_rx can_c_rx flexcan_a ? flexcan_c flexcan receive jcomp jtag enables the jtag tap controller. tck jtag clock input for the on-chip test and debug logic. tdi jtag serial test instruction and data input for the on-chip test and debug logic. tdo jtag serial test data output for the on-chip test logic. tms jtag controls test mode operations for the on-chip test and debug logic. evti nexus evti is an input that is re ad on the negation of reset to enable or disable the nexus debug port. after reset, the evti pin is used to initiate program synchronization messages or generate a breakpoint. evto nexus output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. mcko nexus mcko is a free running clock output to the development tools which is used for timing of the mdo and mseo signals. mdo[3:0] nexus trace message output to development tools. this pin also indicates the status of the crys tal oscillator clock following a power-on reset, when mdo[0] is driven high until the crystal oscillator clock achieves stability and is then negated. mseo [1:0] nexus output pin?indicates the start or end of the variable length message on the mdo pins bootcfg[1] siu ? configuration the bootcfg1 pin is sampled during the assertion of the rstout signal, and the value is used to update the rsr and the bam boot mode the following values are for bootcfg[0:1}: 0 boot from internal flash memory 1 flexcan/esci boot table 6. signal details (continued) signal module or function description
pinout and signal description spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 70/142 doc id 14642 rev 11 ta bl e 7 gives the power/ground segmentation of the spc563mx mcu. each segment provides the power and ground for the given set of i/o pins, and can be powered by any of the allowed voltages regardless of the power on the other segments. wkpcfg siu ? configuration the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), and is sampled 4 clock cycles before the negation of the rstout pin. the value is used to configur e whether the etpu and emios pins are connected to internal weak pull up or weak pull down devices after reset. the value latched on the wkpcfg pin at reset is stored in the reset status register (rsr), and is updated for all reset sources except the debug port reset and software external reset. 0:weak pulldown applied to etpu and emios pins at reset 1:weak pullup applied to etpu and emios pins at reset. etrig[2:3] siu ? eqadc triggers external signal etrigx triggers eqadc cfifox irq[0:15] siu ? external interrupts the irq[0:15] pins connect to t he siu irq inputs. imux select register 1 is used to select the irq[0:15] pins as inputs to the irqs. nmi siu ? external interrupts non-maskable interrupt gpio[n] siu ? gpio configurable general purpose i/o pins. each gpio input and output is separately controlled by an 8-bit input (gpdi) or output (gpdo) register. addi tionally, each gpio pins is configured using a dedicated siu_pcr register. the gpio pins are generally multiplexed with other i/o pin functions. reset siu ? reset the reset pin is an active low input. the reset pin is asserted by an external device during a power-on or external reset. the internal reset sig nal asserts only if the reset pin asserts for 10 clock cycles. assertion of the reset pin while the device is in reset causes the reset cycle to start over. the reset pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the vddeh input pins. the switch point lies between the maximum vil and minimum vih specifications for the vddeh input pins. rstout siu ? reset the rstout pin is an active low output that uses a push/pull configuration. the rstout pin is driven to the low state by the mcu for all internal and external reset sources. there is a delay between initiation of the reset and the assertion of the rstout pin. table 6. signal details (continued) signal module or function description
spc563m64l5, spc563m64l7, spc563m60l5p, spc 563m60l7p pinout and signal description doc id 14642 rev 11 71/142 . table 7. spc563mx power/ground segmentation power segment 100-lqfp pin number 144-lqfp pin number 176-lqfp pin number 208-bga pin number voltage range (1) 1. these are nominal voltages. all vdde and vdde h voltages are ?5%, +10% (vdde 1.62 v to 3.6 v, vddeh 3.0 v to 5.5 v). vdda is +5%, ?10%. i/o pins powered by segment vdda0 3 6 6 b11 5.0 v an[0:7], an[9], an[11], an[16:18], an[21:25], an[27:28], an[30:37], an38, an39, vrl, refbypc, vrh vdde5 ? ? ? t13 1.8 v ? 3.3 v clkout vddeh1 (a,b) 20, 23 24, 34 31, 41 k4 3.3 v ? 5.0 v pckcfg[2], etpu_a[0:31], emios[0:2] vddeh6 (a,b) 56, 66 78, 93 95, 110 f13 3.3 v ? 5.0 v reset , rstout , wkpcfg, bootcfg1, pllref, sck_b, pckcfg[0], can_a_tx, can_a_rx, can_c_tx, can_c_rx, sci_a_tx, sci_a_rx, sci_b_tx, sci_b_rx, sck_b, sin_b, sout_b, dspi_b_pcs_b[0:5], emios[4], emios[8:15], emios[23], xtal, extal vddeh7 (2) 2. the vddeh7 segment may be powered from 3.0 v to 5.0 v for mux address or ssi functions, but must meet the vdda specifications of 4.5 v to 5.25 v for analog input function. 71, 76 102, 113 125, 138 d12 3.3 v ? 5.0 v pckcfg[1], mdo[0:3], evti , evto , mcko, mseo [0:1], tdo, tdi, tms, tck, jcomp, an[12:15] (gpio[98:99], gpio[206:207]) vdde12 (3) vdde7 3. in the calibration package this signal is named vdde12; it is named vdde7 in all other packages. ? ? 16, 119 e13, p6 1.8 v ? 3.3 v cal_addr[12:30], cal_data[0:15], cal_cs [0], cal_cs [2:3], cal_rd_wr , cal_we [0:1], cal_oe , cal_ts, alt_mcko, alt_evto , nexuscfg
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 72/142 doc id 14642 rev 11 4 electrical characteristics this section contains detaile d information on power considerations, dc/ac electrical characteristics, and ac timing specifications for the spc563mxx series of mcus.in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characterist ics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. 4.1 parameter classification the electrical parameters shown in this document are guaranteed by various methods. to provide a better understanding, the classifications listed in ta b l e 8 are used and the parameters are tagged accordingly in the tables. note that only controller characteristics (?cc?) are classified. system requirements (?sr?) are operating conditions that must be provided to ensure normal device operation. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 4.2 maximum ratings table 8. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design c haracterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwi se noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 9. absolute maximum ratings (1) symbol parameter conditions value unit min max v dd sr 1.2 v core supply voltage (2) ? 0.3 1.32 v v flash sr flash core voltage (3) ? 0.3 5.5 v v stby sr sram standby voltage (4) ? 0.3 5.5 v v ddpll sr clock synthesizer voltage ? 0.3 1.32 v v rc33 (5) sr voltage regulator control input voltage ? 0.3 3.6 v
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 73/142 v dda sr analog supply voltage (4) reference to v ssa ? 0.3 5.5 v v dde sr i/o supply voltage (6) ? 0.3 3.6 v v ddeh sr i/o supply voltage (4) ? 0.3 5.5 v v in sr dc input voltage (7) v ddeh powered i/o pads ?1.0 (8) v ddeh +0.3v (9) v v dde powered i/o pads ?1.0 (10) v dde +0.3v (10) v dda powered i/o pads ?1.0 v dda +0.3v v ddreg sr voltage regulator supply voltage (6) ? 0.3 5.5 v v rh sr analog reference high voltage reference to vrl ? 0.3 5.5 v v ss ? v ssa sr v ss differential voltage ? 0.1 0.1 v v rh ? v rl sr v ref differential voltage (6) ? 0.3 5.5 v v rl ? v ssa sr vrl to v ssa differential voltage ? 0.3 0.3 v v sspll ? v ss sr v sspll to v ss differential voltage ? 0.1 0.1 v i maxd sr maximum dc digital input current (11) per pin, applies to all digital pins ? 3 3 ma i maxa sr maximum dc analog input current (12) per pin, applies to all analog pins ?5ma t j sr maximum operating temperature range (13) ? die junction temperature ? 40.0 150.0 o c t stg sr storage temperature range ? 55.0 150.0 o c t sdr sr maximum solder temperature (14) ? 260.0 o c msl sr moisture sensitivity level (15) ?3? 1. functional operating conditions ar e given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guarant eed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. allowed 2 v for 10 hours cumulative time, remaining time at 1.2 v +10%. 3. the v flash supply is connected to v ddeh1 . 4. allowed 6.8 v for 10 hours cumulative time, remaining time at 5 v +10%. 5. the pin named as v rc33 is internally connected to the pads v flash and v rc33 in the lqfp144 package. these limits apply when the internal r egulator is disabled and v rc33 power is supplied externally. 6. all functional non-supply i/ o pins are clamped to v ss and v dde , or v ddeh . 7. ac signal overshoot and undershoot of up to 2.0 v of the i nput voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (i njection current not limi ted for this duration). 8. internal structures hold the volt age greater than ?1.0 v if the injection current limit of 2 ma is met. table 9. absolute maximum ratings (1) (continued) symbol parameter conditions value unit min max
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 74/142 doc id 14642 rev 11 4.3 thermal characteristics 9. internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specificat ion is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 10. internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specificat ion is met (2 ma for all pins) and v dde is within the operating voltage specifications. 11. total injection current for all pins (includi ng both digital and analog) must not exceed 25 ma. 12. total injection current for all anal og input pins must not exceed 15 ma. 13. lifetime operation at these spec ification limits is not guaranteed. 14. solder profile per cdf-aec-q100. 15. moisture sensitivity per jedec test method a112. table 10. thermal characteristics for 100-pin lqfp (1) symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (2) single layer board - 1s 47 c/w r ? ja cc d junction-to-ambient, natural convection (2) four layer board - 2s2p 35 c/w r ? jma cc d junction-to-ambient (@ 200 ft/min) (2) single layer board 37 c/w r ? jma cc d junction-to-ambient (@ 200 ft/min) (2) four layer board 2s2p 29 c/w r ? jb cc d junction-to-board (3) 20 c/w r ? jctop cc d junction-to-case (top) (4) 9c/w ? jt cc d junction-to-package top, natural convection (5) 2c/w 1. thermal characteristics ar e targets based on simulation that are s ubject to change per devic e characterization. 2. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board t hermal resistance determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt. table 11. thermal characteristics for 144-pin lqfp symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (1) single layer board ? 1s 43 c/w r ? ja cc d junction-to-ambient, natural convection (2) four layer board ? 2s2p 35 c/w r ? jma cc d junction-to-ambient (@200 ft/min) (2) single layer board ?1s 34 c/w r ? jma cc d junction-to-ambient (@200 ft/min) (2) four layer board ? 2s2p 29 c/w r ? jb cc d junction-to-board (2) 22 c/w r ? jctop cc d junction-to-case (top) (3) 8c/w ? jt cc d junction-to-package top, natural convection (4) 2c/w
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 75/142 1. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 2. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 4. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt. table 12. thermal characteristics for 176-pin lqfp symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (1) single layer board - 1s 38 c/w r ? ja cc d junction-to-ambient, natural convection (2) four layer board - 2s2p 31 c/w r ? jma cc d junction-to-moving-air, ambient (2) @200 ft./min., single layer board - 1s 30 c/w r ? jma cc d junction-to-moving-air, ambient (2) @200 ft./min., four layer board - 2s2p 25 c/w r ? jb cc d junction-to-board (2) 20 c/w r ? jctop cc d junction-to-case (3) 5c/w ? jt cc d junction-to-package top, natural convection (4) 2c/w 1. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 2. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 4. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt. table 13. thermal characteristics for 208-pin lbga (1) symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection (2),(3) one layer board - 1s 39 c/w r ? jma cc d junction-to-ambient natural convection 2,(4) four layer board - 2s2p 24 c/w r ? ja cc d junction-to-ambient (@200 ft/min) (2),(4) single layer board 31 c/w r ? jma cc d junction-to-ambient (@200 ft/min) (2),(4) four layer board 2s2p 20 c/w r ? jb cc d junction-to-board (5) four layer board - 2s2p 13 c/w r ? jc cc d junction-to-case (6) 6c/w ? jt cc d junction-to-package top natural convection (7) 2c/w 1. thermal characteristics ar e targets based on simulation that are s ubject to change per devic e characterization.
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 76/142 doc id 14642 rev 11 4.3.1 general notes for sp ecifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: equation 1 t j = t a + (r ? ja * p d ) where: t a = ambient temperature for the package ( o c) r ? ja = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. the thermal resistance depends on the: construction of the application board (number of planes) effective size of the board which cools the component quality of the thermal and electrical connections to the planes power dissipated by adjacent components connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias leave the planes virtually disconnected, the ther mal performance is also greatly reduced. as a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. the value obtained on a board with the internal planes is usually within the normal range if the application board has: one oz. (35 micron nominal thickness) internal planes components are well separated overall power dissipation on the board is less than 0.02 w/cm2 the thermal performance of any component depends on the power dissipation of the surrounding components. in addition, the ambient temperature varies widely within the application. for many natural convection and es pecially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. 2. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power diss ipation of other components on the board, and board thermal resistance. 3. per semi g38-87 and jedec jesd51-2 wi th the single-layer board horizontal. 4. per jedec jesd51-6 wi th the board horizontal. 5. thermal resistance between the die and the printed circui t board per jedec jesd51-8. b oard temperature is measured on the top surface of the board near the package. 6. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. 7. thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 77/142 at a known board temperature, the junction temperature is estimated using the following equation: equation 2 t j = t b + (r ? jb * p d ) where: t b = board temperature for the package perimeter ( o c) r ? jb = junction-to-board thermal resistance ( o c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expr essed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: equation 3 r ? ja = r ? jc + r ? ca where: r ? ja = junction-to-ambient thermal resistance ( o c/w) r ? jc = junction-to-case thermal resistance ( o c/w) r ? ca = case to ambient thermal resistance ( o c/w) r ? jc is device related and is not affected by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. this model can be used to generate simple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: equation 4 t j = t t + ( ? jt x p d ) where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w)
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 78/142 doc id 14642 rev 11 the thermal characterization parameter is measured in compliance with the jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. position the thermocouple so that the thermocouple junction rests on the package. place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. pl ace the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 mil-spec and eia/jesd (jedec) specificatio ns are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semitherm, san diego, 1998, pp. 47-54. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications?, electronic packaging and production, pp. 53-58, march 1998. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of semitherm, san diego, 1999, pp. 212-220.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 79/142 4.4 electromagnetic interfer ence (emi) characteristics 4.5 electromagnetic static di scharge (esd) characteristics table 14. emi testing specifications (1) symbol parameter conditions f osc /f bus frequency level (typ) unit radiated emissions v eme device configuration, test conditions and em testing per standard iec61967-2; supply voltage = 5.0v dc, ambient temperature = 25c, worst-case orientation oscillator frequency = 8 mhz; system bus frequency = 80 mhz; no pll frequency modulation 150 khz ? 50 mhz 26 db ? v 50?150 mhz 24 150?500 mhz 24 500?1000 mhz 21 iec level k ? oscillator frequency = 8 mhz; system bus frequency = 80 mhz; 1% pll frequency modulation 150 khz ? 50 mhz 20 db ? v 50?150 mhz 19 150?500 mhz 14 500?1000 mhz 7 iec level l ? 1. iec classification level : l = 24dbuv; k = 30dbuv. table 15. esd ratings (1),(2) symbol parameter conditions value unit ? sr esd for human body model (hbm) ? 2000 v r1 sr hbm circuit description ?1500 ? c sr ? 100 pf ?sr esd for field induced charge model (fcdm) all pins 500 v corner pins 750 ? sr number of pulses per pin positive pulses (hbm) 1 ? negative pulses (hbm) 1 ? ? sr number of pulses ? 1 ? 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. device failure is defined as: ?if after exposure to esd pulses, the device does not m eet the device specification requirements, which includes the complete dc paramet ric and functional testing at room temperature and hot temperature.?
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 80/142 doc id 14642 rev 11 4.6 power management contro l (pmc) and power on reset (por) electrical specifications table 16. pmc operating conditions and external regulators supply voltage id name c parameter min typ max unit 1 jtemp sr ? junction temperature ?40 27 150 c 2 vddreg sr ? pmc 5 v supply voltage vddreg 4.75 (1) 55.25v 3vddsr? core supply voltage 1.2 v vdd when external regulator is used without disabling the internal regulator (pmc unit turned on, lvi monitor active) (2) 1.26 (3) 1.3 1.32 v 3a ? sr ? core supply voltage 1.2 v vdd when external regulator is used with a disabled internal regulator (pmc unit tu rned-off, lvi monitor disabled) 1.14 1.2 1.32 v 4ivddsr? voltage regulator core supply maximum dc output current (4) 400 ? ? ma 5 vdd33 sr ? regulated 3.3 v supply voltage when external regulator is used without disabling the internal regulator (pmc unit turn ed-on, internal 3.3v regulator enabled, lvi monitor active) (5) 3.3 3.45 3.6 v 5a ? sr ? regulated 3.3 v supply voltage when external regulator is used with a disabled internal regulator (pmc unit tu rned-off, lvi monitor disabled) 33.33.6v 6?sr? voltage regulator 3.3 v supply maximum required dc output current 80 ? ? ma 1. during start up operation the mi nimum required voltage to come out of reset state is 4.6 v. 2. an internal regulator controller can be used to regulate core supply. 3. the minimum supply required for the part to exit reset and enter in normal run mode is 1.28 v. 4. the onchip regulator can support a minimum of 400 ma although the worst case core current is 180 ma. 5. an internal regulator can be used to regulate 3.3 v supply. table 17. pmc electrical characteristics id name c parameter min typ max unit notes 1vbgccc nominal bandgap voltage reference ?1.219?v 1a ? cc p untrimmed bandgap reference voltage vbg?7% vbg vbg+6% v 1b ? cc p trimmed bandgap reference voltage (5 v, 27 c) (1) vbg?10mv vbg vbg+10mv v 1c ? cc c bandgap reference temperature variation ? 100 ? ppm /c
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 81/142 1d ? cc c bandgap reference supply voltage variation ?3000? ppm /v 2vddccc nominal vdd core supply internal regulator target dc output voltage (2) ?1.28?v 2a ? cc p nominal vdd core supply internal regulator target dc output voltage variation at power-on reset vdd?6% vdd vdd+10% v 2b ? cc p nominal vdd core supply internal regulator target dc output voltage variation after power-on reset vdd?10 (3) vdd vdd + 3% v 2c ? cc c trimming step vdd ? 20 ? mv 2d ivrcctl cc c voltage regulator controller for core supply maximum dc output current 20 ? ? ma 3 lvi1p2 cc c nominal lvi for rising core supply (4),(5) ?1.160?v 3a ? cc c variation of lvi for rising core supply at power-on reset (5),(6) 1.120 1.200 1.280 v 3b ? cc c variation of lvi for rising core supply after power-on reset (5),(6) lvi1p2?3% lvi1p2 lvi1p2+3% v 3c ? cc c trimming step lvi core supply (5) ?20?mv 3d lvi1p2_h cc c lvi core supply hysteresis (5) ?40?mv 4 por1.2v_r cc c por 1.2 v rising ? 0.709 ? v 4a ? cc c por 1.2 v rising variation por1.2v_r? 35% por1.2v_ r por1.2v_r+ 35% v 4b por1.2v_f cc c por 1.2 v falling ? 0.638 ? v 4c ? cc c por 1.2 v falling variation por1.2v_f? 35% por1.2v_ f por1.2v_f+ 35% v 5 vdd33 cc c nominal 3.3 v supply internal regulator dc output voltage ?3.39?v 5a ? cc p nominal 3.3 v supply internal regulator dc output voltage variation at power- on reset (6) vdd33 ? 8.5% vdd33 vdd3 + 7% v table 17. pmc electrical characteristics (continued) id name c parameter min typ max unit notes
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 82/142 doc id 14642 rev 11 5b ? cc p nominal 3.3 v supply internal regulator dc output voltage variation after power-on reset vdd33 ? 7.5% vdd33 vdd33 + 7% v with internal load up to idd3p3 5c ? cc d voltage regulator 3.3 v output impedance at maximum dc load ?? 2 ? 5d idd3p3 cc p voltage regulator 3.3 v maximum dc output current 80 ? ? ma 5e vdd33 ilim (6) cc c voltage regulator 3.3 v dc current limit ? 130 ? ma 6 lvi3p3 cc c nominal lvi for rising 3.3 v supply (5) ?3.090?v the lvi3p3 specs are also valid for the vddeh lvi 6a ? cc c variation of lvi for rising 3.3 v supply at power-on reset (5) lvi3p3?6% lvi3p3 lvi3p3+6% v see note (7) 6b ? cc c variation of lvi for rising 3.3 v supply after power-on reset (5) lvi3p3?3% lvi3p3 lvi3p3+3% v see note 7 6c ? cc c trimming step lvi 3.3 v (5) ?20?mv 6d lvi3p3_h cc c lvi 3.3 v hysteresis (5) ?60?mv 7 por3.3v_r cc c nominal por for rising 3.3 v supply ?2.07?v the 3.3v por specs are also valid for the vddeh por 7a ? cc c variation of por for rising 3.3 v supply por3.3v_r? 35% por3.3v_ r por3.3v_r+ 35% v 7b por3.3v_f cc c nominal por for falling 3.3 v supply ?1.95?v 7c ? cc c variation of por for falling 3.3 v supply por3.3v_f? 35% por3.3v_ f por3.3v_f+ 35% v 8 lvi5p0 cc c nominal lvi for rising 5 v vddreg supply (5) ?4.290?v 8a ? cc c variation of lvi for rising 5 v vddreg supply at power- on reset (5) lvi5p0?6% lvi5p0 lvi5p0+6% v 8b ? cc c variation of lvi for rising 5 v vddreg supply power-on reset (5) lvi5p0?3% lvi5p0 lvi5p0+3% v 8c ? cc c trimming step lvi 5 v (5) ?20?mv 8d lvi5p0_h cc c lvi 5 v hysteresis (5) ?60?mv table 17. pmc electrical characteristics (continued) id name c parameter min typ max unit notes
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 83/142 9 por5v_r cc c nominal por for rising 5 v vddreg supply ?2.67?v 9a ? cc c variation of por for rising 5 v vddreg supply por5v_r ? 35% por5v_r por5v_r + 50% v 9b por5v_f cc c nominal por for falling 5 v vddreg supply ?2.47?v 9c ? cc c variation of por for falling 5 v vddreg supply por5v_f ? 35% por5v_f por5v_f + 5 0% v 1. the limits will be reviewed after data collection fr om 3 different lots in a full production environment. 2. using external ballast transistor. 3. min range is extended to 10% sinc e lvi1p2 is reprogrammed from 1.2 v to 1.16 v after power-on reset. 4. lvi for falling supply is calculat ed as lvi rising - lvi hysteresis. 5. the internal voltage regulator can be di sabled by tying the vddreg pin to ground. wh en the internal voltage regulator is disabled, the lvi specifications are not applicable because all lvi monitors are disabled. por specifications remain valid when the internal voltage regulator is disabled as long as v ddeh and vdd33 supplies are within the required ranges. 6. this parameter is the ?inrush? current of the internal 3.3v regulator when it is turned on. this spec. is the current at whic h the regulator will go into current limit mode. 7. lvi3p3 tracks dc target variation of internal vdd33 r egulator. minimum and maximum lv i3p3 correspond to minimum and maximum vdd33 dc target respectively. table 17. pmc electrical characteristics (continued) id name c parameter min typ max unit notes
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 84/142 doc id 14642 rev 11 4.6.1 regulator example figure 7. core voltage regulator controller external components preferred configuration there are three options for the bypassing and compensation networks for the 1.2v regulator controller. the component values in the following table are the same for all pmc network requirements. ta bl e 1 9 , ta bl e 2 0 and ta b l e 2 1 show the required component values for the three different options. keep inductance below 20 nh mcu v ddreg v rcctl v dd v ss keep inductance from 5v supply power supply to the transistor collector and vddreg below 1 ? h if not using r c r c c c 5v from c reg required only if r c is used t1 r e r b c b c e c d table 18. required external pmc component values component symbol minimum typical maximum units comment pass transistor t1 njd2873 or bcp68 vddreg capacitor c reg 10 f x7r, -50%/+35% pass transistor collector bypass capacitor c c 13.3 f x7r, -50%/+35% collector resistor (1) r c 1.1 ? 5.6 1. the collector resistor may not be required. it depends on the allowable power dissipation of the pass transistor (t1). ?
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 85/142 the following component configuration is acceptable when using the bcp68 transistor, however, is not recommended for new designs. either option 1 or option 2 should be used for new designs. this option should no t be used with the njd2873 transistor. table 19. network 1 component values component symbol minimum typical maximum units comment transistor emitter bypass capacitance c e 4 x 2.35 4 x 4.7 4 x 6.35 f x7r, -50%/+35% 1 x 5 1 x 10 1 x 13.5 f x7r, -50%/+35% r esr 550m equivalent esr of c e capacitors mcu decoupling capacitor c d 4 x 50 4 x 100 4 x 135 nf x7r, -50%/+35% base "snubber" capacitor c b 1.1 2.2 2.97 f x7r, -50%/+35% base "snubber" resistor r b 6.12 6.8 7.48 10% emitter resistor r e 000 not required (short) ? ? ? table 20. network 2 component values component symbol minimum typical maximum units comment transistor emitter bypass capacitance c e 3 x 2.35 3 x 4.7 3 x 6.35 f x7r, -50%/+35% 1 x 5 1 x 10 1 x 13.5 f x7r, -50%/+35% r esr 550m equivalent esr of c e capacitors mcu decoupling capacitor c d 4 x 50 4 x 100 4 x 135 nf x7r, -50%/+35% base "snubber" capacitor c b 1.1 2.2 2.97 f x7r, -50%/+35% base "snubber" resistor r b 9 10 11 10% emitter resistor r e 0.252 0.280 0.308 not required (short) ? ? ? table 21. network 3 component values component symbol minimum typical maximum units comment transistor emitter bypass capacitance c e 4 x 3.4 4 x 6.8 4 x 9.18 f x7r, -50%/+35% r esr 550m equivalent esr of c e capacitors mcu decoupling capacitor c d 4 x 110 4 x 220 4 x 297 nf x7r, -50%/+35% base "snubber" capacitor c b 1.1 2.2 2.97 f x7r, -50%/+35% ?
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 86/142 doc id 14642 rev 11 4.6.2 recommended power transistors the following npn transistors are recommended for use with the on-chip voltage regulator controller: on semiconductor tm bcp68t1 or njd2873 as we ll as philips semiconductor tm bcp68. the collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator. 4.7 power up/down sequencing there is no power sequencing required among power sources during power up and power down, in order to operate within specification but use of the following sequence is strongly recommended when the internal regulator is bypassed: 5v ? 3.3 v and 1.2 v this is also the normal sequence when the internal regulator is enabled. although there are no power up/down sequencing requirements to prevent issues like latch- up, excessive current spikes, etc., the state of the i/o pins during power up/down varies according to table ta b l e 2 3 for all pins with fast pads and ta bl e 2 4 for all pins with medium, slow and multi-voltage pads. (e) base "snubber" resistor r b 13.5 15 16.5 10% emitter resistor r e 000 not required (short) table 21. network 3 component values (continued) component symbol minimum typical maximum units comment ? ? h fe ( ? ) dc current gain (beta) 60 ? 550 ? p d absolute minimum power dissipation >1.0 (1.5 preferred) w i cmaxdc minimum peak collector current 1.0 a vce sat collector-to-emitter saturation voltage 200?600 (1) 1. adjust resistor at bipolar transistor collector for 3.3 v/5.0 v to avoid vce < vce sat mv v be base-to-emitter voltage 0.4?1.0 v e. if an external 3.3v external regulator is used to supply current to the 1.2v pas s transistor and this supply also supplies current for the other 3.3v supplies, then the 5v supply must always be greater than or equal to the external 3.3v supply. table 23. power sequence pin states for fast pads v dde v rc33 v dd fast (pad_fc) low x x low v dde low x high
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 87/142 4.8 dc electrical specifications v dde v rc33 low high impedance v dde v rc33 v dd functional table 24. power sequence pin states for medium, slow and multi-voltage pads v ddeh v dd medium (pad_msr_hv) slow (pad_ssr_hv) multi-voltage (pad_multv_hv) low x low v ddeh low high impedance v ddeh v dd functional table 23. power sequence pin states for fast pads (continued) v dde v rc33 v dd fast (pad_fc) table 25. dc electrical specifications (1) symbol c parameter conditions value (2) unit min typ max v dd sr ? core supply voltage ? 1.14 ? 1.32 v v dde sr ? i/o supply voltage ? 1.62 ? 3.6 (3) v v ddeh sr ? i/o supply voltage ? 3.0 ? 5.25 v v rc33 sr ? 3.3 v external voltage (4) ?3.0?3.6v v dda sr ? analog supply voltage ?4.75 (5) ?5.25v v indc sr ? analog input voltage (6) ?v ssa ? 0.3 ? v dda +0.3 v v ss ? v ssa sr ? v ss differential voltage ??100?100mv v rl sr ? analog reference low voltage ?v ssa ?v ssa +0.1 v v rl ? v ssa sr ? v rl differential voltage ??100?100mv v rh sr ? analog reference high voltage ?v dda ? 0.1 ? v dda v v rh ? v rl sr ? v ref differential voltage ? 4.75 ? 5.25 v v ddf sr ? flash operating voltage (7) ? 1.14 ? 1.32 v v flash (8) sr ? flash read voltage ? 4.75 ? 5.25 v
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 88/142 doc id 14642 rev 11 v stby sr ? sram standby voltage unregulated mode 0.95 ? 1.2 v regulated mode 2.0 ? 5.5 v ddreg sr ? voltage regulator supply voltage (9) ? 4.75 ? 5.25 v v ddpll sr ? clock synthesizer operating voltage ? 1.14 ? 1.32 v v sspll ? v ss sr ? v sspll to v ss differential voltage ??100?100mv v il_s cc c slow/medium pad i/o input low voltage hysteresis enabled v ss ?0.3 ? 0.35*v ddeh v p hysteresis disabled v ss ?0.3 ? 0.40*v ddeh v il_f cc c fast pad i/o input low voltage hysteresis enabled v ss ?0.3 ? 0.35*v dde v p hysteresis disabled v ss ?0.3 ? 0.40*v dde v il_ls cc c multi-voltage pad i/o input low voltage in low-swing mode (10),(11),(12),(13) hysteresis enabled v ss ?0.3 ? 0.8 v p hysteresis disabled v ss ?0.3 ? 1.1 v il_hs cc c multi-voltage pad i/o input low voltage in high-swing mode hysteresis enabled v ss ?0.3 ? 0.35 v ddeh v p hysteresis disabled v ss ?0.3 ? 0.4 v ddeh v ih_s cc c slow/medium pad i/o input high voltage hysteresis enabled 0.65 v ddeh ?v ddeh +0.3 v p hysteresis disabled 0.55 v ddeh ?v ddeh +0.3 v ih_f cc c fast pad i/o input high voltage hysteresis enabled 0.65 v dde ?v dde +0.3 v p hysteresis disabled 0.55 v dde ?v dde +0.3 v ih_ls cc c multi-voltage pad i/o input high voltage in low-swing mode (10),(11),(12),(13) hysteresis enabled 2.5 ? v ddeh +0.3 v p hysteresis disabled 2.2 ? v ddeh +0.3 table 25. dc electrical specifications (1) (continued) symbol c parameter conditions value (2) unit min typ max
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 89/142 v ih_hs cc c multi-voltage pad i/o input high voltage in high-swing mode (14) hysteresis enabled 0.65 v ddeh ?v ddeh +0.3 v p hysteresis disabled 0.55 v ddeh ?v ddeh +0.3 v ol_s cc p slow/medium multi- voltage pad i/o output low voltage (17),(15) ???0.2*v ddeh v v ol_f cc p fast pad i/o output low voltage (16),(17) ???0.2*v dde v v ol_ls cc p multi-voltage pad i/o output low voltage in low-swing mode (10),(11),(12),(13),( 16) i ol =2ma ? ? 0.6 v v ol_hs cc p multi-voltage pad i/o output low voltage in high-swing mode (16) ???0.2v ddeh v v oh_s cc p slow/medium pad i/o output high voltage (17),(15) ?0.8v ddeh ??v v oh_f cc p fast pad i/o output high voltage (16),(17) ?0.8v dde ??v v oh_ls cc p multi-voltage pad i/o output high voltage in low-swing mode (10),(11),(12),(13),( 16) i oh_ls = 0.5 ma min v ddeh = 4.75 v 2.1 ? 3.7 v v oh_hs cc p multi-voltage pad i/o output high voltage in high-swing mode (16) ?0.8v ddeh ??v v hys_s cc c slow/medium/multi- voltage i/o input hysteresis ? 0.1 * v ddeh ??v v hys_f cc c fast i/o input hysteresis ? 0.1 * v dde ??v v hys_ls cc c low-swing-mode multi-voltage i/o input hysteresis hysteresis enabled 0.25 ? ? v table 25. dc electrical specifications (1) (continued) symbol c parameter conditions value (2) unit min typ max
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 90/142 doc id 14642 rev 11 i dd +i ddpll (18) cc p operating current 1.2 v supplies v dd = 1.32 v, 80 mhz ??195 ma cc p v dd = 1.32 v, 64 mhz ??135 cc p v dd = 1.32 v, 40 mhz ??98 i ddstby cc t operating current 1 v supplies t j =25 o c? ? 80a cc t t j =55 o c? ? 100a i ddstby150 cc p operating current t j =150 o c? ? 700 ? a i ddslow i ddstop cc p v dd low-power mode operating current @ 1.32 v slow mode (19) ??50 ma c stop mode (20) ??50 i dd33 cc t operating current 3.3 v supplies @ 80 mhz v rc33 (4) , (21) ??70ma i dda i ref i ddreg cc p operating current 5.0 v supplies @ 80 mhz v dda ??30 ma p analog reference supply current ??1.0 cv ddreg ??70 i ddh1 i ddh6 i ddh7 i dd7 i ddh9 i dd12 cc d operating current v dde (22) supplies @ 80 mhz v ddeh1 ?? see note (22) ma dv ddeh6 ?? dv ddeh7 ?? dv dde7 ?? dv ddeh9 ?? dv dde12 ?? i act_s cc c slow/medium i/o weak pull up/down current (23) 3.0 v ? 3.6 v 15 ? 95 ? a p 4.75 v ? 5.25 v 35 ? 200 i act_f cc d fast i/o weak pull up/down current (23) 1.62 v ? 1.98 v 36 ? 120 ? a d 2.25 v ? 2.75 v 34 ? 139 d 3.0 v ? 3.6 v 42 ? 158 table 25. dc electrical specifications (1) (continued) symbol c parameter conditions value (2) unit min typ max
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 91/142 i act_mv_pu cc c multi-voltage pad weak pullup current v ddeh = 3.0?3.6 v (10) , pad_multv_h v, all process corners, high swing mode only 10 ? 75 ? a p 4.75 v ? 5.25 v 25 ? 200 i act_mv_pd cc c multivoltage pad weak pulldown current v ddeh = 3.0?3.6 v (10) , pad_multv_h v, all process corners, high swing mode only 10 ? 60 ? a p 4.75 v ? 5.25 v 25 ? 200 i inact_d cc p i/o input leakage current (24) ? ?2.5 ? 2.5 ? a i ic cc t dc injection current (per pin) ? ?1.0 ? 1.0 ma i inact_a cc p analog input current, channel off, an[0:7], an38, an39 (25) ??250?250 na p analog input current, channel off, all other analog pins (anx) (25) ??150?150 c l cc d load capacitance (fast i/o) (26) dsc(pcr[8: 9]) = 0b00 ??10 pf d dsc(pcr[8: 9]) = 0b01 ??20 d dsc(pcr[8: 9]) = 0b10 ??30 d dsc(pcr[8: 9]) = 0b11 ??50 c in cc d input capacitance (digital pins) ???7pf c in_a cc d input capacitance (analog pins) ???10pf table 25. dc electrical specifications (1) (continued) symbol c parameter conditions value (2) unit min typ max
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 92/142 doc id 14642 rev 11 c in_m cc d input capacitance (digital and analog pins (27) ) ???12pf r pupd200k cc p weak pull-up/down resistance (28),(29) 200 k ? option ? 130 ? 280 k ? r pupdmatch cc c 200k ? option ?2.5 2.5 % r pupd100k cc p weak pull-up/down resistance (28),(29) 100 k ? option ?65?140k ? r pupdmatch cc c 100k ? option ?2.5 2.5 % r pupd5k cc d weak pull-up/down resistance (28) 5k ? option 5v5% supply 1.4 ? 7.5 k ? t a (t l to t h )sr? operating temperature range - ambient (packaged) ? ?40.0 ? 125.0 ? c ?sr? slew rate on power supply pins ???50v/ms 1. these specifications are des ign targets and subject to ch ange per device characterization. 2. tbd: to be defined. 3. v dde must be lower than v rc33 , otherwise there is additional leakage on pins supplied by v dde . 4. these specifications apply when v rc33 is supplied externally , after disabling the internal regulator (v ddreg = 0). 5. adc is functional with 4 v ? v dda ? 4.75 v but with derated accuracy. this means the adc will continue to function at full speed with no bad behavior, but the accuracy will be degraded. 6. internal structures hold the input voltage less than v dda + 1.0 v on all pads powered by v dda supplies, if the maximum injection current specification is met (3 ma for all pins) and v dda is within the operatin g voltage specifications. 7. the v ddf supply is connected to v dd in the package substrate. this specificat ion applies to calibration package devices only. 8. v flash is only available in the calibration package. 9. regulator is functional, with derated perform ance, with supply voltage down to 4.0 v. 10. multi-voltage pads (type pad_multv_hv) must be su pplied with a power supply between 4.75 v and 5.25 v. 11. the slew rate (src) setting must be 0b11 when in low-swing mode. 12. while in low-swing mode there are no restri ctions in transition ing to high-swing mode. 13. pin in low-swing mode can accept a 5 v input. 14. pin in low-swing mode can accept a 5 v input. 15. characterization based capability: ioh_s = {6, 11.6} ma and iol_s = {9.2, 17.7} ma for {slow, medium} i/o with vddeh=4.5 v; ioh_s = {2.8, 5.4} ma and iol_s = {4.2, 8.1} ma for {slow, medium} i/o with vddeh=3.0 v 16. characterizati on based capability: ioh_f = {12, 20, 30, 40} ma and iol_f = {24, 40, 50, 65} ma for {00, 01,10, 11} drive mode with vdde=3.0 v; ioh_f = {7, 13, 18, 25} ma and iol_f = {18, 30, 35, 50} ma for {00, 01, 10, 11} drive mode with vdde=2.25 v; ioh_f = {3, 7, 10, 15} ma and iol_f = {12, 20, 27, 35} ma for {00, 01, 10, 11} drive mode with vdde=1.62 v 17. all vol/voh values 100% tested with 2 ma load. table 25. dc electrical specifications (1) (continued) symbol c parameter conditions value (2) unit min typ max
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 93/142 18. run mode as follows: system clock = 40/60/80 mhz + fm 2% code executed from flash memory adc0 at 16 mhz with dma enabled adc1 at 8 mhz emios pads toggle in pwm mode with a rate between 100 khz and 500 khz etpu pads toggle in pwm mode with a rate between 10 khz and 500 khz can configured for a bit rate of 500 khz dspi configured in master mode with a bit rate of 2 mhz esci transmission configured with a bit rate of 100 khz 19. bypass mode, system clock at 1 mhz (usi ng system clock divider), pll shut down, cpu running simple executive code, 4 x adc conversion every 10 ms, 2 pwm c hannels at 1 khz, all other modules stopped. 20. bypass mode, system clock at 1 mhz (u sing system clock divider), cpu stopped, pit running, all other modules stopped. 21. when using the internal regulator only, a bypass capacitor should be connected to this pin. exte rnal circuits should not be powered by the internal regulator. the internal regula tor can be used as a refer ence for an external debugger. 22. power requirements for each i/o segment are dependent on t he frequency of operation and load of the i/o pins on a particular i/o segment, and the voltage of the i/o segment. see table 26 for values to calculate power dissipation for specific operation. the total power cons umption of an i/o segment is the sum of the individual power consumptions for each pin on the segment. 23. absolute value of current, measured at v il and v ih . 24. weak pull up/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types: fast (pad_fc). 25. maximum leakage occurs at maximum o perating temperature. leakage current decr eases by approximately one-half for each 8 to 12 o c, in the ambient temperature range of 50 to 125 o c. applies to pad types: pad_a and pad_ae. 26. applies to clkout, external bus pins, and nexus pins. 27. applies to the fck, sdi, sdo, and sds pins. 28. this programmable option applies onl y to eqadc differential input channel s and is used for biasing and sensor diagnostics. 29. when the pull-up and pull-down of the same nominal 200 k ? or 100 k ? value are both enabled, assuming no interference from external devices, the re sulting pad voltage will be 0.5*v dde 2.5%
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 94/142 doc id 14642 rev 11 4.9 i/o pad current specifications note: spc563mxx devices use two sets of i/o pads (5 v and 3.3 v). see ta bl e 4 and ta b l e 5 in section 3.6, signal summary , for the pad type associated with each signal. the power consumption of an i/o segment depends on the usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin current can be calculated from ta bl e 2 6 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in ta b l e 2 6 . table 26. i/o pad average i dde specifications (1) pad type symbol c period (ns) load (2) (pf) v dde (v) drive/slew rate select i dde avg (ma) (3) i dde rms (ma) slow i drv_ssr_hv cc d 37 50 5.25 11 9 ? cc d 130 50 5.25 01 2.5 ? cc d 650 50 5.25 00 0.5 ? cc d 840 200 5.25 00 1.5 ? medium i drv_msr_hv cc d 24 50 5.25 11 14 ? cc d 62 50 5.25 01 5.3 ? cc d 317 50 5.25 00 1.1 ? cc d 425 200 5.25 00 3 ? fast i drv_fc cc d 10 50 3.6 11 22.7 68.3 cc d 10 30 3.6 10 12.1 41.1 cc d 10 20 3.6 01 8.3 27.7 cc d 10 10 3.6 00 4.44 14.3 cc d 10 50 1.98 11 12.5 31 cc d 10 30 1.98 10 7.3 18.6 cc d 10 20 1.98 01 5.42 12.6 cc d 10 10 1.98 00 2.84 6.4 multiv (high swing mode) i drv_multv_hv cc d 15 50 5.25 11 21.2 (4) ? cc d 30 50 5.25 10 ? (5) ? cc d 50 50 5.25 01 6.2 4 ? cc d 300 50 5.25 00 1.1 4 ? cc d 300 200 5.25 00 4.0 4 ? multiv (low swing mode) i drv_multv_hv cc d 15 30 5.25 11 20.2 (6) ? cc d 30 30 5.25 11 na ? 1. numbers from simulations at best case process, 150 c. 2. all loads are lumped. 3. average current is for pad configured as output only.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 95/142 4.9.1 i/o pad vrc33 current specifications the power consumption of the vrc33 supply is dependent on the usage of the pins on all i/o segments. the power consumption is the sum of all output pin v rc33 currents for all i/o segments. the output pin v rc33 current can be calculated from ta bl e 2 7 based on the voltage, frequency, and load on all medium, slow, and multv_hv pins. the output pin vrc33 current can be calculated from ta bl e 2 8 based on the voltage, frequency, and load on all fast pins. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in ta bl e 2 7 and ta bl e 2 8 . 4. ratio from 5.5 v pad spec to 5.25 v data sheet. 5. not specified. 6. low swing mode is not a strong function of v dde . table 27. i/o pad v rc33 average i dde specifications (1) pad type symbol c period (ns) load (2) (pf) slew rate select i dd33 avg (a) i dd33 rms (a) slow i drv_ssr_hv cc d 100 50 11 0.8 235.7 cc d 200 50 01 0.04 87.4 cc d 800 50 00 0.06 47.4 cc d 800 200 00 0.009 47 medium i drv_msr_hv cc d 40 50 11 2.75 258 cc d 100 50 01 0.11 76.5 cc d 500 50 00 0.02 56.2 cc d 500 200 00 0.01 56.2 multiv (3) (high swing mode) i drv_multv_hv cc d 40 50 11 2.75 258 cc d 100 50 01 0.11 76.5 cc d 500 50 00 0.02 56.2 cc d 500 200 00 0.01 56.2 multiv (4) (low swing mode) i drv_multv_hv cc d 40 30 11 2.75 258 cc d 100 30 11 0.11 76.5 cc d 500 30 11 0.02 56.2 cc d 500 30 11 0.01 56.2 1. these are typical values that are estimated from simulation and not test ed. currents apply to output pins only. 2. all loads are lumped. 3. average current is for pad configured as output only. 4. in low swing mode, multi-voltage pads (pad_multv _hv) must operate in highest slew rate setting.
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 96/142 doc id 14642 rev 11 4.9.2 lvds pad specifications lvds pads are implemented to support the ms c (microsecond channel) protocol which is an enhanced feature of the dspi module. the lvds pads are compliant with lvds specifications and support data rates up to 50 mhz. table 28. v rc33 pad average dc current (1) 1. these are typical values that ar e estimated from simulation and not te sted. currents apply to output pins only. pad type symbol c period (ns) load (2) (pf) 2. all loads are lumped. v rc33 (v) v dde (v) drive select i dd33 avg (a) i dd33 rms (a) fast i drv_fc cc d 10 50 3.6 3.6 11 2.35 6.12 cc d 10 30 3.6 3.6 10 1.75 4.3 cc d 10 20 3.6 3.6 01 1.41 3.43 cc d 10 10 3.6 3.6 00 1.06 2.9 cc d 10 50 3.6 1.98 11 1.75 4.56 cc d 10 30 3.6 1.98 10 1.32 3.44 cc d 10 20 3.6 1.98 01 1.14 2.95 cc d 10 10 3.6 1.98 00 0.95 2.62 table 29. dspi lvds pad specification (1) # characteristic symbol c condition min. value typ. value max. value unit data rate 4 data frequency f lv d s c l k cc d 50 mhz driver specs 5 differential output voltage v od cc p src=0b00 or 0b11 150 430 mv cc p src=0b01 90 340 cc p src=0b10 155 480 6 common mode voltage (lvds), v os v os cc p 0.8 1.2 1.6 v 7 rise/fall time t r /t f cc d 2 ns 8 propagation delay (low to high) t plh cc d 4 ns 9 propagation delay (high to low) t phl cc d 4 ns 10 delay (h/l), sync mode t pdsync cc d 4 ns 11 delay, z to normal (high/low) t dz cc d 500 ns
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 97/142 4.10 oscillator and pllmrfm electrical characteristics 12 diff skew itphla-tplhbi or itplhb-tphlai t skew cc d 0.5 ns termination 13 trans. line (differential zo) cc d 95 100 105 ? 14 temperature cc d ?40 150 ? c 1. these are typical values that are estimated from simulation. table 29. dspi lvds pad specification (1) (continued) # characteristic symbol c condition min. value typ. value max. value unit table 30. pllmrfm electrical specifications (1) (v ddpll =1.14 v to 1.32 v, v ss = v sspll = 0 v, t a = t l to t h ) symbol c parameter conditions value unit min max f ref_crystal f ref_ext cc d pll reference frequency range (2) crystal reference 4 20 mhz c external reference 4 80 f pll_in cc p phase detector input frequency range (after pre-divider) ?416mhz f vco cc p vco frequency range (3) ?256512mhz f sys cc c on-chip pll frequency (2) ?1680mhz f sys cc t system frequency in bypass mode (4) crystal reference 4 20 mhz p external reference 0 80 t cyc cc d system clock period ? ? 1 / f sys ns f lorl f lorh cc d loss of reference frequency window (5) lower limit 1.6 3.7 mhz d upper limit 24 56 f scm cc p self-clocked mode frequency (6),(7) ?1.275mhz c jitter cc t clkout period jitter (8),(9),(10), (11) peak-to-peak (clock edge to clock edge) f sys maximum ?5 5 %f clk out t long-term jitter (avg. over 2 ms interval) ?6 6 ns t cst cc t crystal start-up time (12), (13) ??10ms v ihext cc t extal input high voltage crystal mode (14) , 0.8 ? vxtal ? 1.5v vxtal + 0.4 ? v t external reference (14), (15) v rc33 /2 + 0.4 v rc33
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 98/142 doc id 14642 rev 11 v ilext cc t extal input low voltage crystal mode (14) , 0.65 ? vxtal ? 1.25v ? vxtal ? 0.4 v t external reference (14), (15) 0 v rc33 /2 ? 0.4 ? cc t xtal load capacitance (12) 4mhz 5 30 pf 8mhz 5 26 12 mhz 5 23 16 mhz 5 19 20 mhz 5 16 t lpll cc p pll lock time (12), (16) ??200 ? s t dc cc t duty cycle of reference ?4060% f lck cc t frequency lock range ? ?6 6 % f sys f ul cc t frequency un-lock range ? ?18 18 % f sys f cs f ds cc d modulation depth center spread 0.25 4.0 %f sys d down spread ?0.5 ?8.0 f mod cc d modulation frequency (17) ??100khz 1. all values given are initial des ign targets and subject to change. 2. considering operation with pll not bypassed. 3. f vco is calculated as follows: ? in legacy mode f vco =(f crystal / (prediv + 1)) * (4 * (mfd + 4)) ? in enhanced mode fvco = (f crystal / (eprediv + 1)) * (emfd + 4) 4. all internal registers retain data at 0 hz. 5. ?loss of reference frequency? window is the reference frequency range outside of which the pll is in self clocked mode. 6. self clocked mode frequency is the frequency that the pll op erates at when the reference frequency falls outside the f lor window. 7. f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 8. this value is determined by the crystal manufacturer and board design. 9. jitter is the average deviation from t he programmed frequency measured over t he specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal osci llator frequency increase the c jitter percentage for a given interval. 10. proper pc board layout procedures must be followed to achieve specifications. 11. values are with frequency modulati on disabled. if frequency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 12. this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this pll, load capacitors should not exceed these limits. for a 20 mhz crysta l the maximum load should be 17 pf. 13. proper pc board layout procedures must be followed to achieve specifications. 14. this parameter is guaranteed by design rather than 100% tested. 15. v ihext cannot exceed v rc33 in external reference mode. 16. this specification applies to the period required for the p ll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). table 30. pllmrfm electrical specifications (1) (v ddpll =1.14 v to 1.32 v, v ss = v sspll = 0 v, t a = t l to t h ) (continued) symbol c parameter conditions value unit min max
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 99/142 4.11 temperature sensor el ectrical characteristics 4.12 eqadc electrica l characteristics note: adc performance is affected by several environmental elements, such as quality of the input signal source, presence of noise sources and quality of the pcb layout. the dc or static parameters (dnl, inl, offset, gain, and tue) are measured using methods that provide a very accurate evaluation using averaging. the ac or dynamic parameters (snr, thd, sfdr, sinad) are determined using a full scale peak-peak sinewave of 1khz frequency at the input of the adc. 17. modulation depth will be attenuated from depth setti ng when operating at modulation frequencies above 50khz. table 31. temperature sensor electrical characteristics symbol c parameter conditions value unit min typical max ?ccc temperature monitoring range ?40 ? 150 c ? cc c sensitivity ? 6.3 ? mv/c ? cc p accuracy t j = ?40 to 150 c ?10 ? 10 c table 32. eqadc conversion specifications (operating) symbol c parameter value unit min max f adclk sr ? adc clock (adclk) frequency 2 16 mhz cc cc d conversion cycles 2 + 13 128 + 14 adclk cycles t sr cc c stop mode recovery time (1) ?10 ? s ? cc d resolution (2) 1.25 ? mv offnc cc c offset error without calibration 0 160 counts offwc cc c offset error with calibration ?4 4 counts gainnc cc c full scale gain error without calibration ?160 0 counts gainwc cc c full scale gain error with calibration ?4 4 counts i inj cc t disruptive input injection current (3), (4), (5), (6) ?3 3 ma e inj cc t incremental error due to injection current (6),(7),(8) ?4 4 counts tue8 cc c total unadjusted error (tue) at 8 mhz (9) ?4 4 counts tue16 cc c total unadjusted error at 16 mhz (10) ?8 8 counts snr cc t signal to noise ratio (11) 55.2 db thd cc t total harmonic distorsion 70.0 db
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 100/142 doc id 14642 rev 11 sfdr cc t spurious free dynamic range 65.0 db sinad cc t signal to noise and distorsion 55.0 db enob cc t effective number of bits 8.8 counts gainvga1 cc ? variable gain amplifier accuracy (gain=1) (12) cc c inl 8 mhz adc ?4 4 counts (13) cc c 16 mhz adc ?8 8 counts cc c dnl 8mhz adc ?3 (14) 3 (14) counts cc c 16 mhz adc ?3 (14) 3 (14) counts gainvga2 cc ? variable gain amplifier accuracy (gain=2) (12) cc d inl 8 mhz adc ?5 5 counts cc d 16 mhz adc ?8 8 counts cc d dnl 8 mhz adc ?3 3 counts cc d 16 mhz adc ?3 3 counts gainvga4 cc ? variable gain amplifier accuracy (gain=4) (12) cc d inl 8 mhz adc ?7 7 counts cc d 16 mhz adc ?8 8 counts cc d dnl 8 mhz adc ?4 4 counts cc d 16 mhz adc ?4 4 counts diff max cc c maximum differential voltage (danx+ - danx-) or (danx- - danx+) pregain set to 1x setting ? (vrh - vrl)/2 v diff max2 cc c pregain set to 2x setting ? (vrh - vrl)/4 v diff max4 cc c pregain set to 4x setting ? (vrh - vrl)/8 v diff cmv cc c differential input common mode voltage (danx- + danx+)/2 (15) (vrh - vrl)/2 - 5% (vrh - vrl)/2 + 5% v 1. stop mode recovery time is the time from the setting of either of the enable bits in the adc control register to the time tha t the adc is ready to perform conversions.del ay from power up to full accuracy = 8 ms. 2. at v rh ? v rl = 5.12 v, one count = 1.25 mv. without using pregain. 3. below disruptive current c onditions, the channel being stress ed has conversion values of 0x3ff for analog inputs greater then v rh and 0x0 for values less then v rl . other channels are not affected by non-disruptive conditions. 4. exceeding limit may cause conversion error on stressed channels and on unstressed channels. transitions within the limit do not affect device reliabil ity or cause permanent damage. 5. input must be current limited to the value specified. to deter mine the value of the required current-limiting resistor, calcu late resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 6. condition applies to two adjacen t pins at injection limits. 7. performance expected with production silicon. 8. all channels have same 10 k ? spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 101/142 9. tue is tested by averaging 10 samples. 10. tue is tested by averaging three samples. 11. these values can be significantly im proved by using three samples of averaging. input frequency of 1 khz was used as the reference for the signal to noise ratio. 12. variable gain is controlled by setting the pre_gain bits in the adc_acr1 -8 registers to select a gain factor of ? 1, ? 2, or ? 4. settings are for differential input only. tested at ? 1 gain. values for other settings are guaranteed by as indicated. 13. at v rh ? v rl = 5.12 v, one lsb = 1.25 mv. 14. guaranteed 10-bit monotonicity. 15. voltages between vrl and vrh will not cause damage to the pins . however, they may not be converted accurately if the differential voltage is above the maximum differential voltage. in addition, conversion errors may occur if the common mode voltage of the differential signal violates the di fferential input common mode voltage specification.
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 102/142 doc id 14642 rev 11 4.13 platform flash controller electrical characteristics 4.14 flash memory elect rical characteristics table 33. apc, rwsc, wwsc settings vs. frequency of operation (1) 1. illegal combinations exist, all entries must be taken from the same row target max frequency (mhz) apc (2) 2. apc must be equal to rwsc rwsc (2) wwsc 20 000 000 01 40 001 001 01 64 010 010 01 80 011 011 01 all 111 111 111 table 34. program and erase specifications symbol parameter min value typical value (1) initial max (2) max (3) unit t dwprogram p double word (64 bits) program time (4) ?2250500 ? s t 16kpperase p 16 kb block pre-program and erase time ? 300 500 5000 ms t 32kpperase p 32 kb block pre-program and erase time ? 400 600 5000 ms t 64kpperase p 64 kb block pre-program and erase time ? 600 900 5000 ms t 128kpperase p 128 kb block pre-program and erase time ? 800 1300 7500 ms 1. typical program and erase ti mes assume nominal supply values and operati on at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage. 3. the maximum program & erase times occu r after the specified number of progra m/erase cycles. thes e maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. table 35. flash module life symbol parameter conditions value unit min typ p/e c number of program/erase cycles per block for 16 kbyte blocks over the operating temperature range (t j ) ? 100,000 ? cycles p/e c number of program/erase cycles per block for 32 and 64 kbyte blocks over operating temperature range (t j ) ? 10,000 ? cycles p/e c number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) ? 1,000 ? cycles
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 103/142 retention c minimum data retention at 85 c average ambient temperature (1) blocks with 0 ? 1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 5?years 1. ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. table 35. flash module life (continued) symbol parameter conditions value unit min typ
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 104/142 doc id 14642 rev 11 4.15 ac specifications 4.15.1 pad ac specifications table 36. pad ac spec ifications (5.0 v) (1),(2) name c output delay (ns) (3),(4) low-to-high / high- to-low rise/fall edge ( ) 4 , (5) drive load (pf) src/dsc min max min max msb,lsb medium (6),(7),(8) cc d 4.6/3.7 12/12 2.2/2.2 7/7 50 11 (9) cc d 13/10 32/32 9/9 22/22 200 n/a 10 (10) cc d 12/13 28/34 5.6/6 15/15 50 01 cc d 23/23 52/59 11/14 31/31 200 cc d 69/71 152/165 34/35 74/74 50 00 cc d 95/90 205/220 44/51 96/96 200 slow (8),(11) cc d 7.3/5.7 19/18 4 .4/4.3 14/14 50 11 (9) cc d 24/19 58/58 17/15 42/42 200 n/a 10 (10) cc d 26/27 61/69 13/13 34/34 50 01 cc d 49/45 115/115 27/23 61/61 200 cc d 137/142 320/330 72/74 164/164 50 00 cc d 182/172 420/420 90/85 200/200 200 multiv (12) (high swing mode) cc d 4.1/3.6 10.3/8.9 3.28/2.98 8/8 50 11 (9) cc d 10.4/10.2 24.2/23.6 12.7/11.54 29/29 200 n/a 10 (10) cc d 8.38/6.11 16/12.9 5 .48/4.81 11/11 50 01 cc d 15.9/13.6 31/28.5 14.6/13.1 31/31 200 cc d 61.7/10.4 92.2/24 .3 42.0/12.2 63/63 50 00 cc d 85.5/37.3 132.6/ 78.9 57.7/46.4 85/85 200 multiv (low swing mode) cc d 2.31/2.34 7.62/6.3 3 1.26/1.67 7/7 30 11 (9) fast (13) n/a pad_i_hv (14) cc d 0.5/0.5 1.9/1.9 0.3/0.3 1.5/1.5 0.5 n/a pull_hv cc d na 6000 ? 5000/5000 50 n/a 1. these are worst case values that are estimated from simula tion and not tested. values in the table are simulated at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v dde = 1.62 v to 1.98 v, v ddeh = 4.5 v to 5.25 v, t a = t l to t h . 2. tbd: to be defined.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 105/142 3. this parameter is supplied for reference and is not guaranteed by design and not tested. 4. delay and rise/fall are measured to 20% or 80% of the respective signal. 5. this parameter is guaranteed by characteri zation before qualification rather than 100% tested. 6. in high swing mode, high/low swing pad vol and voh values ar e the same as those of the slew controlled output pads 7. medium slew-rate controlled output buffer. contains an input buffer and weak pullup/pulldown. 8. output delay is shown in figure 8 . add a maximum of one system clock to the out put delay for delay with respect to system clock. 9. can be used on the tester. 10. this drive select value is not supported. if selected, it will be approximately equal to 11. 11. slow slew-rate controlled output buffer. c ontains an input buffer and weak pullup/pulldown. 12. selectable high/low swing io pad with selectable slew in high swing mode only. 13. fast pads are 3.3 v pads. 14. stand alone input buffer. also has weak pull-up/pull-down. table 37. pad ac spec ifications (3.3 v) (1) pad type c output delay (ns) (2),(3) low-to-high / high- to-low rise/fall edge (ns) (3),(4) drive load (pf) src/dsc min max min max msb,lsb medium (5),(6),(7) cc d 5.8/4.4 18/17 2 .7/2.1 10/10 50 11 (8) cc d 16/13 46/49 11.2/8.6 34/34 200 n/a 10 (9) cc d 14/16 37/45 6.5/6.7 19/19 50 01 cc d 27/27 69/82 15/13 43/43 200 cc d 83/86 200/210 38/38 86/86 50 00 cc d 113/109 270/285 53/46 120/120 200 slow (7),(10) cc d 9.2/6.9 27/28 5 .5/4.1 20/20 50 11 cc d 30/23 81/87 21/16 63/63 200 n/a 10 (9) cc d 31/31 80/90 15.4/15.4 42/42 50 01 cc d 58/52 144/155 32/26 82/85 200 cc d 162/168 415/415 80/82 190/190 50 00 cc d 216/205 533/540 106/95 250/250 200
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 106/142 doc id 14642 rev 11 multiv (7),(11) (high swing mode) cc d 3.7/3.1 10/10 30 11 (8) cc d 46/49 37/37 200 n/a 10 (9) cc d 32 15/15 50 01 cc d 72 46/46 200 cc d 210 100/100 50 00 cc d 295 134/134 200 fast cc d 2.5/2.5 1.2/1.2 10 00 cc d 2.5/2.5 1.2/1.2 20 01 cc d 2.5/2.5 1.2/1.2 30 10 cc d 2.5/2.5 1.2/1.2 50 11 (8) pad_i_hv (12) cc d 0.5/0.5 3/3 0.4/0.4 1.5/1.5 0.5 n/a pull_hv cc d na 6000 5000/5000 50 n/a 1. these are worst case values that are estimated from simula tion and not tested. the values in the table are simulated at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v dde = 3 v to 3.6 v, v ddeh = 3 v to 3.6 v, t a = t l to t h . 2. this parameter is supplied for reference and is not guaranteed by design and not tested. 3. delay and rise/fall are measured to 20% or 80% of the respective signal. 4. this parameter is guaranteed by characteri zation before qualification rather than 100% tested. 5. in high swing mode, high/low swing pad vol and voh values ar e the same as those of the slew controlled output pads 6. medium slew-rate controlled output buffer. contains an input buffer and weak pullup/pulldown. 7. output delay is shown in figure 8 . add a maximum of one system clock to the out put delay for delay with respect to system clock. 8. can be used on the tester 9. this drive select value is not supported. if selected, it will be approximately equal to 11. 10. slow slew-rate controlled output buffer. c ontains an input buffer and weak pullup/pulldown. 11. slow slew-rate controlled output buffer. c ontains an input buffer and weak pullup/pulldown. 12. stand alone input buffer. also has weak pull-up/pull-down. table 37. pad ac spec ifications (3.3 v) (1) (continued) pad type c output delay (ns) (2),(3) low-to-high / high- to-low rise/fall edge (ns) (3),(4) drive load (pf) src/dsc min max min max msb,lsb
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 107/142 figure 8. pad output delay table 38. pad ac specifications (1.8 v) pad type c output delay (ns) (1),(2) low-to-high / high- to-low rise/fall edge (ns) (3) drive load (pf) src/dsc min max min max msb,lsb fast cc d 3.0/3.0 2.0/1.5 10 00 cc d 3.0/3.0 2.0/1.5 20 01 cc d 3.0/3.0 2.0/1.5 30 10 cc d 3.0/3.0 2.0/1.5 50 11 (4) 1. this parameter is supplied for reference and is not guaranteed by design and not tested. 2. delay and rise/fall are measured to 20% or 80% of the respective signal. 3. this parameter is guaranteed by characteri zation before qualification rather than 100% tested. 4. can be used on the tester. v dde /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 108/142 doc id 14642 rev 11 4.16 ac timing 4.16.1 ieee 1149.1 interface timing figure 9. jtag test clock input timing table 39. jtag pin ac electrical characteristics (1) # symbol c characteristic min. value max. value unit 1t jcyc cc d tck cycle time 100 ? ns 2t jdc cc d tck clock pulse width 40 60 ns 3t tckrise cc d tck rise and fall times (40% ? 70%) ? 3 ns 4t tmss, t tdis cc d tms, tdi data setup time 5 ? ns 5t tmsh, t tdih cc d tms, tdi data hold time 25 ? ns 6t tdov cc d tck low to tdo data valid ?23ns 7t tdoi cc d tck low to tdo data invalid 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 20 ns 9t jcmppw cc d jcomp assertion time 100 ? ns 10 t jcmps cc d jcomp setup time to tck low 40 ? ns 11 t bsdv cc d tck falling edge to output valid ? 50 ns 12 t bsdvz cc d tck falling edge to output valid out of high impedance ?50ns 13 t bsdhz cc d tck falling edge to output high impedance ? 50 ns 14 t bsdst cc d boundary scan input valid to tck rising edge 50 ? ns 15 t bsdht cc d tck rising edge to boundary scan input invalid 50 ? ns 1. jtag timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.25 v with multi-voltage pads programmed to low- swing mode, t a = t l to t h, and c l = 30 pf with dsc = 0b10, src = 0b00. t hese specifications apply to jtag boundary scan only. see table 40 for functional specifications. tck 1 2 2 3 3
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 109/142 figure 10. jtag test access port timing figure 11. jtag jcomp timing tck 4 5 6 7 8 tms, tdi tdo tck jcomp 9 10
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 110/142 doc id 14642 rev 11 figure 12. jtag boundary scan timing 4.16.2 nexus timing tck output signals input signals output signals 11 12 13 14 15 table 40. nexus debug port timing (1) # symbol c characteristic min. value max. value unit 1t mcyc cc d mcko cycle time 2 (2),(3) 8t cyc 1a t mcyc cc d absolute minimum mcko cycle time 100 (4) ?ns 2t mdc cc d mcko duty cycle 40 60 % 3t mdov cc d mcko low to mdo data valid (5) ? 0.1 0.2 t mcyc 4t mseov cc d mcko low to mseo data valid (5) 0.1 0.2 t mcyc 6t evtov cc d mcko low to evto data valid (5) ? 0.1 0.2 t mcyc 7t evtipw cc d evti pulse width 4.0 ? t tcyc 8t evtopw cc d evto pulse width 1 ? t mcyc
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 111/142 figure 13. nexus output timing 9t tcyc cc d tck cycle time 4 (6),(7) ?t cyc 9a t tcyc cc d absolute minimum tck cycle time 100 (8) ?ns 10 t tdc cc d tck duty cycle 40 60 % 11 t ntdis cc d tdi data setup time 5 ? ns 12 t ntdih cc d tdi data hold time 25 ? ns 13 t ntmss cc d tms data setup time 5 ? ns 14 t ntmsh cc d tms data hold time 25 ? ns 15 t jov cc d tck low to tdo data valid 10 20 ns 1. all nexus timing relative to mcko is measured from 50 % of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.25 v with multi-voltage pads programmed to low-swing mode, t a = tl to th, and cl = 30 pf with dsc = 0b10. 2. achieving the absolute minimum mcko cy cle time may require setting the mcko di vider to more than its minimum setting (npc_pcr[mcko_div] depending on the ac tual system frequency being used. 3. this is a functionally allowable featur e. however, this may be limited by the ma ximum frequency specified by the absolute minimum mcko period specification. 4. this may require setting the mcko divider to more t han its minimum setting (npc_pcr[mcko_div]) depending on the actual system frequency being used. 5. mdo, mseo , and evto data is held valid until next mcko low cycle. 6. achieving the absolute minimum tck cycl e time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7. this is a functionally allowable featur e. however, this may be limited by the ma ximum frequency specified by the absolute minimum tck period specification. 8. this may require a maximum clock speed (system frequency / 8) that is less than the maximu m functional capability of the design (system frequency / 4) depending on the actual system frequency being used. table 40. nexus debug port timing (1) (continued) # symbol c characteristic min. value max. value unit 1 2 4 6 mcko mdo mseo evto output data valid 3
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 112/142 doc id 14642 rev 11 figure 14. nexus event trigger and test clock timings figure 15. nexus tdi, tms, tdo timing tck 9 7 8 evti evto 8 7 tck 11 12 15 tms, tdi tdo 13 14
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 113/142 4.16.3 calibration bus interface timing table 41. calibration bus operation timing (1) # symbol c characteristic 66 mhz (ext. bus) (2) unit notes min max 1t c cc p clkout period 15.2 ? ns signals are measured at 50% v dde . 2t cdc cc d clkout duty cycle 45% 55% t c 3t crt cc d clkout rise time ? (3) ns 4t cft cc d clkout fall time ? (3) ns 5t coh cc d clkout posedge to output signal invalid or high z(hold time) addr[8:31] cs[0:3] data[0:31] oe rd_wr ts we [0:3]/be [0:3] 1.0 (4) /1.5 ? ns hold time selectable via siu_eccr[ebts] bit: ebts=0: 1.0ns ebts=1: 1.5ns 6t cov cc d clkout posedge to output signal valid (output delay) addr[8:31] cs[0:3] data[0:31] oe rd_wr ts we [0:3]/be [0:3] ?6.0 (4) /7.0 ns output valid time selectable via siu_eccr[ebts] bit: ebts=0: 5.5ns ebts=1: 6.5ns 7t cis cc d input signal valid to clkout posedge (setup time) data[0:31] 5.0 ? ns 8t cih cc d clkout posedge to input signal invalid (hold time) data[0:31] 1.0 ? ns 9t apw cc d ale pulse width (5) 6.5 ? ns 10 t aai cc d ale negated to address invalid (5) 3?ns 1. calibration bus timing specified at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v dde = 1.62 v to 3.6 v (unless stated otherwise), t a = t l to t h , and c l = 30 pf with dsc = 0b10. 2. the external bus is limited to half the speed of the internal bus. the maxi mum external bus frequency is 66 mhz.
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 114/142 doc id 14642 rev 11 figure 16. clkout timing 3. refer to fast pad timing in table 37 and table 38 (different values for 3.3 v vs. 1.8 v). 4. the ebts=0 timings are only valid/ tested at v dde =2.25?3.6 v, whereas ebts=1 timings are valid/tested at 1.6?3.6 v. 5. measured at 50% of ale. 1 2 2 3 4 clkout vdde/2 vol_f voh_f
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 115/142 figure 17. synchronous output timing 6 5 5 clkout bus 5 output signal output vdde/2 vdde/2 vdde/2 vdde/2 6 5 output signal vdde/2 6
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 116/142 doc id 14642 rev 11 figure 18. synchronous input timing figure 19. ale signal timing 7 8 clkout input bus 7 8 input signal vdde/2 vdde/2 vdde/2 ipg_clk clkout ale ts addr data a/d 9 10
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 117/142 4.16.4 emios timing 4.16.5 dspi timing table 42. emios timing (1) # symbol c characteristic min. value max. value unit 1t mipw cc d emios input pulse width 4 ? t cyc 2t mopw cc d emios output pulse width 1 ? t cyc 1. emios timing specified at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.25 v, t a = t l to t h , and c l = 50 pf with src = 0b00. table 43. dspi timing (1),(2) # symbol c characteristic 40 mhz 64 mhz 80 mhz unit min. max. min. max. min. max. 1t sck cc d sck cycle time (3),(4) 48.8 ns 5.8 ms 28.4 ns 3.5 ms 24.4 ns 2.9 ms ? 2t csc cc d pcs to sck delay (5) 46 ? 26 ? 22 ? ns 3t asc cc d after sck delay (6) 45 ? 25 ? 21 ? ns 4t sdc cc d sck duty cycle ( ? t sc ) ? 2 ( ? t sc ) + 2 ( ? t sc ) ? 2 ( ? t sc ) + 2 ( ? t sc ) ? 2 ( ? t sc ) + 2 ns 5t a cc d slave access time (ss active to sout driven) ?25?25?25ns 6t dis cc d slave sout disable time (ss inactive to sout high-z or invalid) ?25?25?25ns 7t pcsc cc d pcsx to pcss time4?4?4?ns 8t pasc cc d pcss to pcsx time5?5?5?ns 9t sui cc data setup time for inputs d master (mtfe = 0) 20 ? 20 ? 20 ? ns dslave 2?2?2? d master (mtfe = 1, cpha = 0) (7) ?4?6?8? d master (mtfe = 1, cpha = 1) 20 ? 20 ? 20 ?
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 118/142 doc id 14642 rev 11 10 t hi cc data hold time for inputs d master (mtfe = 0) ?4 ? ?4 ? ?4 ? ns dslave 7?7?7? d master (mtfe = 1, cpha = 0) (7) 45 ? 25 ? 21 ? d master (mtfe = 1, cpha = 1) ?4 ? ?4 ? ?4 ? 11 t suo cc data valid (after sck edge) dmaster (mtfe = 0)?6?6?6 ns dslave ?25?25?25 d master (mtfe = 1, cpha=0) ?45?25?21 d master (mtfe = 1, cpha=1) ?6?6?6 12 t ho cc data hold time for outputs d master (mtfe = 0) ?5 ? ?5 ? ?5 ? ns d slave 5.5 ? 5.5 ? 5.5 ? d master (mtfe = 1, cpha = 0) 8?4?3? d master (mtfe = 1, cpha = 1) ?5 ? ?5 ? ?5 ? 1. all dspi timing specifications use t he fastest slew rate (src = 0b11) on pad ty pe m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate. dspi timing is specified at vddeh = 3.0?5.25 v, ta = tl to th, and cl = 50 pf with src = 0b11. 2. speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 42 mhz parts allow for 40 mhz syste m clock + 2% fm; 66 mhz parts allow for a 64 mhz system clock + 2% fm, and 82 mhz parts allow for 80 mh z system clock + 2% fm. 3. the minimum dspi cycle time restricts the baud rate sele ction for given system clock ra te. these numbers are calculated based on two spc563mxx devices comm unicating over a dspi link. 4. the actual minimum sck cycle ti me is limited by pad performance. 5. the maximum value is programmable in dspi_ctarx[pssck] and dspi_ctarx[cssck]. 6. the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc]. 7. this number is calculated assuming the smpl_pt bitfield in dspi_mcr is set to 0b10. table 43. dspi timing (1),(2) (continued) # symbol c characteristic 40 mhz 64 mhz 80 mhz unit min. max. min. max. min. max.
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 119/142 figure 20. dspi classic spi timing ? master, cpha = 0 figure 21. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 these numbers reference ta b l e 4 3 . data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) these numbers reference ta b l e 4 3 .
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 120/142 doc id 14642 rev 11 figure 22. dspi classic spi timing ? slave, cpha = 0 figure 23. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) these numbers reference ta bl e 4 3 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) these numbers reference ta bl e 4 3 .
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 121/142 figure 24. dspi modified transfer format timing ? master, cpha = 0 figure 25. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) these numbers reference ta bl e 4 3 . pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) these numbers reference ta bl e 4 3 .
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 122/142 doc id 14642 rev 11 figure 26. dspi modified transfer format timing ? slave, cpha =0 figure 27. dspi modified transfer format timing ? slave, cpha =1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 these numbers reference ta bl e 4 3 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) these numbers reference ta bl e 4 3 .
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p electrical characteristics doc id 14642 rev 11 123/142 figure 28. dspi pcs strobe (pcss ) timing 4.16.6 eqadc ssi timing pcsx 7 8 pcss table 44. eqadc ssi timing characteri stics (pads at 3.3 v or at 5.0 v) (1) cload = 25pf on all outputs. pad drive strength set to maximum. # symbol c rating min typ max unit 1f fck cc d fck frequency (2), (3) 1/17 f sys_clk 1 ? 2 f sys_clk hertz 1t fck cc d fck period (t fck = 1/ f fck ) 2 t sys_clk 17t sys_clk seconds 2t fckht cc d clock (fck) high time t sys_clk ? 6.5 9 * t sys_clk ? 6.5 ns 3t fcklt cc d clock (fck) low time t sys_clk ? 6.5 8 * t sys_clk ? 6.5 ns 4t sds_ll cc d sds lead/lag time ?7.5 +7.5 ns 5t sdo_ll cc d sdo lead/lag time ?7.5 +7.5 ns 6t dvfe cc d data valid from fck falling edge (t fcklt+ t sdo_ll ) 1ns 7t eq _ su cc d eqadc data setup time (inputs) 22 ns 8t eq_ho cc d eqadc data hold time (inputs) 1 ns 1. ss timing specified at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v ddeh = 4.5 v to 5.25 v, t a = t l to t h , and c l =50pf with src = 0b00. 2. maximum operating frequency is highly dependent on track delays, master pad dela ys, and slave pad delays. 3. fck duty is not 50% when it is generated through th e division of the system clock by an odd number.
electrical characteristics spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 124/142 doc id 14642 rev 11 figure 29. eqadc ssi timing 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 5 4 4 3 1 3 2 1 2 fck sds sdo external device data sample at sdi eqadc data sample at fck falling edge fck rising edge
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p packages doc id 14642 rev 11 125/142 5 packages 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
packages spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 126/142 doc id 14642 rev 11 5.2 package mechanical data 5.2.1 lqfp100 figure 30. lqfp100 package mechanical drawing d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p packages doc id 14642 rev 11 127/142 5.2.2 lqfp144 symbol dimensions millimeters inches (1) 1. values in inches are conver ted from millimeters (mm) and rounded to four decimal digits. min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 (2),(3) 2. lqfp stands for low profile quad flat pack age. low profile: body thickness (a2 = 1.40 mm) 3. exact shape of each corner is optional. 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 03.57 03.57 ccc (4) 4. tolerance 0.080 0.0031
packages spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 128/142 doc id 14642 rev 11 figure 31. lqfp144 package mechanical drawing d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p packages doc id 14642 rev 11 129/142 table 45. lqfp144 mechanical data symbol dimensions millimeters inches (1) 1. values in inches are conver ted from millimeters (mm) and rounded to four decimal digits. min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 (2),(3) 2. lqfp stands for low profile plastic quad flat pac kage. low profile: a2 (body thickness) = 1.4 mm 3. exact shape of each corner is optional. 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 ? 17.500 ? ? 0.6890 ? e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 ? 17.500 ? ? 0.6890 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 03.57 03.57 ccc (4) 4. tolerance 0.08 0.003
packages spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 130/142 doc id 14642 rev 11 5.2.3 lqfp176 figure 32. lqfp176 package mechanical drawing ccc c s e a ting pl a ne c aa2 a1 c 0.25 mm g au ge pl a ne hd d a1 l l1 k 8 9 88 ehe 45 44 e 1 176 pin 1 identific a tion b 1 33 1 3 2 1t_me zd ze
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p packages doc id 14642 rev 11 131/142 table 46. lqfp176 mechanical data symbol dimensions millimeters inches (1) 1. values in inches are conver ted from millimeters (mm) and rounded to four decimal digits. min typ max min typ max a ? ? 1.600 ? ? 0.063 a1 0.050 ? 0.150 0.002 ? ? a2 1.350 ? 1.450 0.053 ? 0.057 b 0.170 ? 0.270 0.007 ? 0.011 c 0.090 ? 0.200 0.004 ? 0.008 d 23.900 ? 24.100 0.941 ? 0.949 e 23.900 ? 24.100 0.941 ? 0.949 e ? 0.500 ? ? 0.020 ? hd 25.900 ? 26.100 1.020 ? 1.028 he 25.900 ? 26.100 1.020 ? 1.028 l (2) 2. l dimension is measured at gauge pl ane at 0.25 above the seating plane. 0.450 ? 0.750 0.018 ? 0.030 l1 ? 1.000 ? ? 0.039 ? zd ? 1.250 ? ? 0.049 ? ze ? 1.250 ? ? 0.049 ? ccc ? ? 0.080 ? ? 0.003
packages spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 132/142 doc id 14642 rev 11 5.2.4 lbga208 figure 33. lbga208 package mechanical drawing
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p packages doc id 14642 rev 11 133/142 table 47. lbga208 mechanical data symbol dimensions millimeters inches (1) 1. values in inches are conver ted from millimeters (mm) and rounded to four decimal digits. min typ max min typ max a (2) 2. lbga stands for low profile ball grid array. low profil e: the total profile height (dim a) is measured from the seating plane to the top of the component. the ma ximum total package height is calculated by the following methodology: a2 typ + a1 typ + ? (a1 2 + a3 2 + a4 2 tolerance values). low profile: 1.20 mm < a ? 1.70 mm ? ? 1.70 ? ? 1.55 a1 0.30 ? ? 0.45 0.50 0.55 a2 ? 1.085 ? 1.03 1.085 1.14 a3 ? 0.30 ? 0.26 0.30 0.34 a4 ? ? 0.80 0.77 0.785 0.80 b (3) 3. the typical ball diameter before mounting is 0.60 mm. 0.50 0.60 0.70 0.55 0.60 0.65 d 16.80 17.00 17.20 16.90 17.00 17.10 d1 ? 15.00 ? ? 15.00 ? e 16.80 17.00 17.20 16.90 17.00 17.10 e1 ? 15.00 ? ? 15.00 ? e ? 1.00 ? ? 1.00 ? f ? 1.00 ? ? 1.00 ? ddd ? ? 0.20 ? ? 0.20 eee (4) 4. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindric al tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. ? ? 0.25 ? ? 0.25 fff (5),(6) 5. the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respective zone eee abov e. the axis of each ball must lie simultaneously in both tolerance zones. 6. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. ? ? 0.10 ? ? 0.10
ordering information spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 134/142 doc id 14642 rev 11 6 ordering information figure 34. commercial product code structure memory core family y = tray r = tape and reel a = 80 mhz b = 64 mhz c = 40 mhz o = full version p = phantom c = ?40 to 125 c b2 = lbga208 l3 = lqfp100 l5 = lqfp144 l7 = lqfp176 54 = 768 kbytes 60 = 1 mbyte 64 = 1.5 mbytes m = spc563m family 3 = e200z3 spc56 = power architecture-90nm temperature package frequency spc56 64 3m c l5 a example code: product identifier version o conditioning r
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p revision history doc id 14642 rev 11 135/142 7 revision history ta bl e 4 8 summarizes revisions to this document. table 48. document revision history date revision changes 18-apr-2008 1 initial release 16-may-2008 2 ? maximum amount of flash increased from 1 mb to 1.5 mb. flash memory type has changed. rev. 1 and later devices use lc flash instead of fl flash. ? additional packages offered?now incl udeslqfp100 and lqfp176. please note that the pinouts can vary for the same package depending on the amount of flash memory included in the device. ? device comparison table added. ? feature details section added ? signal summary table expanded. now includes pcr register numbers and signal selection values and pin numbers for all production packages. ? electrical characteristics updated. ? dspi timing data added for 40 mhz and 60 mhz. ? thermal characteristics data updated. data added for 100- and 176-pin packages. ? dspi lvds pad specifications added. 16-mar-2009 3 electrical characteristics updated ? flash memory electrical characteristics updated for lc flash ? power management control (pmc) and powe r on reset (por) specifications updated ? emi characteristics data added ? maximum ratings updated ? i/o pad current specifications updated ? i/o pad vrc33 current specifications added ? temperature sensor electrical characteristics added pad type added to ?voltage? column of signal summary table many signal names have changed to make them more understandable ? dspi: pcs_c[n] is now dspi_c_pcs[n]; sout_c is now dspi_c_sout, sin_c is now dspi_c_sin, and sck_c is now dspi_c_sck ? can: cntxb is now can_b_tx and cnrxb is now can_b_rc ? sci: rxdb is now sci_b_rx and txdb is now sci_b_tx ? in cases where multiple instan ces of the same ip block is incorporated into the device, e.g., 2 sci blocks, the above nomenclature applies to all blocks ?no connect? pins on pinouts clarified ? pins labelled ?nic? have no internal connection and should be tied to ground ? pins labelled ?nc? are not functional pins but may be connected to internal circuits they are to be left floating some of the longer multiplexed signal names appearing on pinouts have been moved to the inside of the package body to avoid having to use smaller fonts
revision history spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 136/142 doc id 14642 rev 11 16-mar-2009 3 orderable parts table updated part number decoder added 15-dec-2009 4 208-pin lbga ballmap for the spc563m60 (1024 kb flash memory) has changed. power management control (pmc) and power on reset (por) electrical specifications updated temperature sensor data added specifications now indicate ho w each controller characteristic parameter is guaranteed. i/o pad current spec ifications updated i/o pad vrc33 current specifications updated pad ac characteristics updated vga gain specifications added to eqadc electrical characteristics dc electrical specifications updated: ? footnote added to rpupd100k and rpup d200k: when the pull-up and pull-down of the same nominal 200 k ? or 100 k ? value are both enabled, assuming no interference from other devices, the resulting pad voltage will be 0.5 vdde 2.5% ?i ol condition added to v ol_ls . ?i oh condition added to v oh_ls . ? minimum v oh_ls is 2.3 v (was 2.7 v). ? separate i ddpll removed from i dd spec because we can only measure i dd +i ddpll . i dd increased by 15 ma (to 195 ma) to account for i ddpll . i dd now documented as i dd +i ddpll . footnote added detailing runtim e configuration used to measure i dd +i ddpll . ? specifications for i ddstby and i ddstby150 reformatted to make more clear. ?v stby is now specified by two ranges. the area in between those ranges is indeterminate. lvds pad specifications updated: ? min value for v od at src=0b01 is 90 mv (was 120); and 160 mv (was 180) at src = 0b10 changes to signal properties table: ? vdde7 removed as voltage segment from calibration bus pins. calibration bus pins are powered by vdde12 only. ? gpio[139] and gpio[87] pins changed to medium pads ? some signal names have changed on 176-pin qfp package pinout: ?cal_x? signals renamed to ?alt_x?. table 48. document revision history (continued) date revision changes
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p revision history doc id 14642 rev 11 137/142 15-dec-2009 4 changes to pad types table: ? column heading changed from ?voltage? to ?supply voltage? ? multiv pad high swing mode voltage changed to 3.0 v ? 5.25 v (was 4.5 v ? 5.25 v) ? multiv pad low swing mode voltage changed to 4.5 v ? 5.25 v (was 3.0 v ? 3.6 v) signal details table added power/ground segmentation table added 15-apr-2010 5 updates to features list: ? mmu is 16-entry (previously noted as 8-entry) ? ecsm features include single-bit error correction reporting ? etpu2 is object code compatib le with previous etpu versions updates to feature details: ? programming feature: etpu2 channel flags can be tested pinout/ballmap changes: 100 pin lqfp package: ? pin 31 is now vddeh1b (was vddeh4a) ? pin 43 is now vddeh6a (was vddeh4b) 144 pin lqfp package: ? pin 46 is now vddeh1b (was vddeh4a) ? pin 61 is now vddeh6a (was vddeh4b) 176 pin lqfp package (1.5m devices) ? pin 55 is now vddeh1b (was vddeh4a) ? pin 74 is now vddeh6a (was vddeh4b) 176 pin lqfp package (1.5m devices) ? pin 55 is now vddeh1b (was vddeh4a) ? pin 74 is now vddeh6a (was vddeh4b) 208 ball bga package (all devices) ball n9 changed to nc (no connect) (was vddeh6) table 48. document revision history (continued) date revision changes
revision history spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 138/142 doc id 14642 rev 11 15-apr-2010 5 (cont.) changes to calibration ball names on devices with 1 mb flash memory: ? cal_mdo0 changed to alt_mdo0 ? cal_mdo1 changed to alt_mdo1 ? cal_mdo2 changed to alt_mdo2 ? cal_mdo3 changed to alt_mdo3 ? cal_mseo0 changed to alt_mseo0 ? cal_mseo1 changed to alt_mseo1 ? cal_evti changed to alt_evti ? cal_evto changed to alt_evto ? cal_mcko changed to alt_mcko power/ground segment changes: ? the following pins are on vdde7 i/o segment only on the 208-ball bga package: alt_mdo[0:3], alt_mseo[0:1], alt_evti, alt_evto, alt_mcko. ? power segments vddeh4, vddeh4a and vddeh4b have been removed. clkout power segment is vdde5 (was vdde12) thermal characteristics for 176-pin lqfp updated (all parameter values) pmc operating conditions and external re gulators supply voltage specifications updated ? (2) pmc 5 v supply voltage vddreg min value is 4.5 v (was 4.75 v) pmc electrical characterist ics specifications updated ? (1d) bandgap reference supply voltage variation is 3000 ppm/v (was 1500 ppm/v) ? (5a) nominal 3.3 v supply internal regulator dc output voltage variation at power-on reset min value is vdd33-8.5% (was unspecified previously) ? (5a) nominal 3.3 v supply internal regulator dc output voltage variation at power-on reset max value is vdd3+7% (was unspecified previously) ? (9a) variation of por for rising 5 v vddreg supply max value is por5v_r + 50% (was por5v_r + 35%) ? (9c) variation of por for falling 5 v vddreg supply max value is por5v_f + 50% (was por5v_f + 35%) ? (9c) note added: minimum loading (<10 ma) for reading trim values from flash, powering internal rc oscillator, and io consumption during por. ?core voltage regulator controller exter nal components preferred configuration? circuit diagram updated table 48. document revision history (continued) date revision changes
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p revision history doc id 14642 rev 11 139/142 15-apr-2010 5 (cont.) changes to dc electrical specifications: ? footnote added to v dde . v dde must be less than v rc33 or there is additional leakage on pins supplied by v dde . ? low range sram standby voltage (v stby ) minimum changed to 0.95 v (was 0.9 v) ? low range sram standby voltage (v stby ) maximum changed to 1.2 v (was 1.3 v) ? high range sram standby voltage (v stby ) minimum changed to 2.0 v (was 2.5 v) ?v il_ls max value (hysteresis disabled) changed to 0.9 v (was 1.1 v) ?v oh_ls min value changed to 2 v (was 2.3 v) ?i ddslow max value is 50 ma ?i ddstop max value is 50 ma ?i dda max value is 30 ma (was 15.0 ma) ?i dd4 and v ddeh4 removed?they no longer exist i/o pad average i dde specifications table updated i/o pad v rc33 average i dde specifications table updated lvds pad specifications table updated ?v os min value is 0.9 v (was 1.075 v) ?v os max value is 1.6 v (was 1.325 v) updates to pllmrfm elec trical specifications: ? maximum values for xtal load capacitan ce added. the maximum value varies with frequency. ? for a 20 mhz crystal the maximum load should be 17 pf. temperature sensor accuracy is 10 c (was 5 c) updates to eqadc conversion specifications (operating): ? offset error without calibration max value is 160 (was 100) ? full scale gain error without calibration min value is ?160 (was ?120) changes to platform flash controller electrical characteristics: ? apc, rwsc, wwsc settings vs. frequency of operation table updated changes to flash memory specifications: ?t bkprg 64 kb specification removed ( not present in this device) ?t 64kpperase specification added ? flash module life p/e spec for 32 kbyte blocks also applies to 64 kbyte blocks pad ac specifications (3.3 v) table updated lbga208 package is no longer offered for 1024 kb (spc563m60) devices table 48. document revision history (continued) date revision changes
revision history spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p 140/142 doc id 14642 rev 11 19-apr-2010 6 updated ?core voltage regulator controller external components preferred configuration? figure. ? clarification added to note: emitter and collector capacitors (6.8 ? f and 10 ? f) should be matched (same type) and esr should be lower than 200 mw. (added emphasis that only 6.8 ? f emitter capacitors need to be matched with collector capacitor. ?220 ? f emitter capacitors changed to 220 nf. 03-feb-2011 7 no specification or product information changes: ? mechanical outline drawings section re named to ?packages? and restructured. ? ecopack section added. 04-feb-2011 8 removed the 208 bga package from the device-summary table. revised the ?pmc operating conditions and external regulators supply voltage? table. revised the ?pmc electrical characteristics? table. revised the pad ac specifications. revised the ?dc electrical specifications? table. revised the ?dspi lvds pad specification? table: revised the ?pllmrfm electrical specifications? table. change to ?temperature sensor elec trical characteristics? table: ? accuracy is guaranteed by production test revised the ?eqadc conversion specifications (operating)? table. changes to ?calibration bus operation timing? table: ? clkout period is guaranteed by prod uction test. all other parameters are guaranteed by design changes to ?program and erase specifications? table in ?flash memory electrical characteristics? section. ? deleted bank program (512kb) (t bkprg ) parameter ? typ p/e values added for 32- and 64 kb blocks and for 128 kb blocks. changes to recommended operating characteristics for external power transistor: ? vcesat should be between 200 and 600 mv ? vbe should be 0.4v to 1.0v changes to ?apc, rwsc, wwsc settings vs. frequency of operation? table in platform flash controller electrical characteristics section: ? target max frequency of 60 mhz changed to 64 mhz. removed footnote 8 from vddeh in maximum ratings. table 48. document revision history (continued) date revision changes
spc563m64l5, spc563m64l7, spc563m60l5p, spc563m60l7p revision history doc id 14642 rev 11 141/142 04-feb-2011 8 (cont.) deleted engineering names for pads in power up/down sequencing section changed ?sin_c? to dspi_c_sin? and ?sck_c? to dspi_c_sck? on 144 pin lqfp package. updated the ?electromagnetic interference characteristics? table to reflect new parameter levels, test conditions. in the ?apc, rwsc, wwsc settings vs. frequency of operation? table, changed 82 mhz entry for wwc from ?11? to ?01?, added an extra row for ?all 111 111 11? replaced all of the mechanical drawings along with associated parameter tables. updated the ordering information. in the ?dc electrical specifications? table, changed r pupdmatch from +/- 1% to +/- 2.5%. 06-jun-2012 9 in section 4.6.1, regulator example ? updated , figure 7 ?core voltage regulator controller external components preferred configuration? to show r c , r b , r e , c c , c b , c e , c d and c reg . ? added ta bl e 1 8 ?required external pmc component values?, ta bl e 1 9 ?network 1 component values?, ta b l e 2 0 ?network 2 component values? and ta bl e 2 1 ?network 3 component values?. updated ta b l e 2 : number of emios channels changed from ?8? to ?16? for spc563m54p. in section 4.2, maximum ratings , ta b l e 9 ?v flash maximum value changed from 3.6v to 5.5v and changed table note3 to: ?the v flash supply is connected to v ddeh ? ? removed table note 4, ?allowed 5.3 v for 10 hours cumulative time, remaining time at 3.3 v +10%? in section 4.12, eqadc elec trical characteristics : ? added note. in ta bl e 3 2 , additional five parameters added (s nr, thd, sfdr, sinad and enob) and added footnotes # 9,10 and 11. 03-oct-2012 10 added rpns spc563m60l5p, spc563m60l7p in the title and in ta b l e 1 . 17-sep-2013 11 updated disclaimer table 48. document revision history (continued) date revision changes
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